Sebastien Bourdeauducq
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
Yann Sionneau
286092b62e
Raise exception when not using correct boolean operators
2014-10-27 19:40:22 +08:00
Florent Kermarrec
86abb253c8
flow/actor/Endpoint: clean up __getattr__
2014-10-22 09:35:30 +08:00
Florent Kermarrec
37031e3a2f
DMAWriteController: fix Demultiplexer layout
2014-10-20 23:58:16 +08:00
Florent Kermarrec
07c33279c2
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
Florent Kermarrec
ff688fb2f9
_Endpoint: allow direct access of payload elements
2014-10-20 23:09:56 +08:00
Florent Kermarrec
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
Florent Kermarrec
22507b117c
bank: add re to CSRStorage
...
being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
2014-10-16 17:43:41 +08:00
Sebastien Bourdeauducq
15f67b30d0
genlib/fsm: make first fsm.act() the reset state, even when using after_*/before_* methods before fsm.act
2014-09-29 19:38:58 +08:00
Florent Kermarrec
e03091e7e2
add generic CRCEngine, CRC32, CRCInserter and CRCChecker
...
CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
2014-09-26 11:42:10 +08:00
Florent Kermarrec
a03570ccca
flow/actor: fix eop direction
2014-09-23 00:14:58 +08:00
Florent Kermarrec
66054af7bb
flow/actor: add packetized parameter for Sink and Source
2014-09-22 23:45:28 +08:00
Florent Kermarrec
967b73bef3
actorlib/structuring: add reverse parameter to Unpack and Pack
2014-09-22 23:41:40 +08:00
Sebastien Bourdeauducq
6c9810532b
genlib/fifo/SyncFIFOBuffered: replace not supported
2014-09-17 19:59:13 +08:00
Sebastien Bourdeauducq
4cacf97088
genlib/fifo: same 'level' semantics between SyncFIFOBuffered and FWFT SyncFIFO
2014-09-17 19:58:43 +08:00
Florent Kermarrec
09ebcc47aa
setup.py: fix README filename
2014-09-12 08:19:05 +08:00
Sebastien Bourdeauducq
264bc61e04
genlib/fifo: add replace command to sync FIFO
2014-09-10 21:19:15 +08:00
Sebastien Bourdeauducq
b15c357a10
README: more markdown fixes
2014-09-10 20:52:19 +08:00
Sebastien Bourdeauducq
4bdc550924
README: markdown fixes
2014-09-10 20:51:17 +08:00
Sebastien Bourdeauducq
92e51f10b1
README: use markdown
2014-09-10 20:49:49 +08:00
Sebastien Bourdeauducq
325ffdc6c6
actorlib/spi: remove unneeded import
2014-09-08 18:48:54 +08:00
Florent Kermarrec
c1e12c3346
actorlib/spi: remove EventManager from DMAController
2014-09-08 11:34:21 +08:00
Robert Jordens
0bac463780
sim/icarus: add vpi directory to module search path
...
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
2014-09-07 16:49:12 +08:00
Robert Jordens
3d84a7a9de
cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic
2014-09-07 16:49:12 +08:00
Robert Jordens
11f58862db
test_cordic: stop spewing out numbers
2014-09-07 16:49:12 +08:00
Robert Jordens
11fedfc825
doc: update for NetworkX refactoring
2014-09-07 16:48:46 +08:00
Robert Jordens
7518a7b0c0
examples/dataflow: adapt to new simple MultiDiGraph implementation
2014-09-07 16:48:46 +08:00
Robert Jordens
4def6ec391
flow/network: replace NetworkX MultiDiGraph with simple implementation
2014-09-07 16:48:46 +08:00
Robert Jordens
8489604142
examples/dataflow/dma: fix simulation, run it for 100 cycles
2014-09-07 16:48:46 +08:00
Robert Jordens
683643266f
cordic: vivado is bad at inferring compact adder/subtractor logic
2014-09-04 15:25:34 +08:00
Robert Jordens
4328122a9c
vivado: add more reporting
2014-09-04 15:25:34 +08:00
Robert Jordens
7c19e43444
vivado: mode batch to prevent vivado from opening tcl shell on error
2014-09-04 15:25:34 +08:00
Sebastien Bourdeauducq
f21e05025d
platforms/kc705: use jtaghs1_fast cable
2014-09-03 17:29:26 +08:00
Florent Kermarrec
644fa8ec55
kc705: enable DCI termination on DDR3
2014-09-02 10:54:38 +08:00
Sebastien Bourdeauducq
402c7db63c
platforms/kc705: read the configuration flash faster (ISE only)
2014-08-22 18:44:10 +08:00
Sebastien Bourdeauducq
cb5894b33c
platforms: add -w option to bitgen_opt
2014-08-22 18:26:25 +08:00
Florent Kermarrec
7f4e51253e
kc705: add spiflash pins
2014-08-22 10:32:58 +08:00
Florent Kermarrec
c19d134978
vivado: enable bitstream compression (optional)
2014-08-21 20:22:08 +08:00
Robert Jordens
bd232f3f61
fhdl.structure: do not permit clock domain names that start with numbers
2014-08-18 11:01:56 +08:00
Robert Jordens
ac2e961618
fhdl.structure: remove unused imports
2014-08-18 11:01:56 +08:00
Robert Jordens
6036fffef2
Signal.__getitem__: raise TypeError and IndexError when appropriate
2014-08-18 11:01:56 +08:00
Robert Jordens
b3d69913cd
Signal.like: pass kwargs
2014-08-18 11:01:56 +08:00
Robert Jordens
7e77254c57
vivado: make tcl a list of commands, add reporting
2014-08-18 11:01:56 +08:00
Sebastien Bourdeauducq
c61f96588a
mibuild/programmer: remove unneeded needs_flash_proxy attr
2014-08-09 14:28:15 +08:00
Sebastien Bourdeauducq
54c63275e0
platforms/kc705: remove DDR3 multirank pins
2014-08-09 10:56:59 +08:00
Sebastien Bourdeauducq
60706e4b70
bus/dfi: add CKE and RESET_N
2014-08-09 10:56:08 +08:00
Sebastien Bourdeauducq
5fb221e7d9
typo
2014-08-06 23:58:09 +08:00
Sebastien Bourdeauducq
7ebf08db5e
mibuild/xilinx: connect CE on reset synchronizer FFs
2014-08-06 23:51:50 +08:00
Sebastien Bourdeauducq
b124a98d92
genlib: add reset synchronizer
2014-08-06 19:38:37 +08:00
Sebastien Bourdeauducq
4d382328d5
mibuild/xilinx: share more code between ISE and Vivado, use special overrides with Vivado, merge xilinx_tools into xilinx_common
2014-08-06 19:26:00 +08:00
