Florent Kermarrec
|
c088cd5d22
|
cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices.
|
2020-11-05 19:43:11 +01:00 |
Florent Kermarrec
|
3e47a6e48b
|
get_data_mod: fix error message when module not found (pythondata modules are named only with "-" and not "_").
|
2020-11-05 15:58:32 +01:00 |
Florent Kermarrec
|
65f19b5c4a
|
integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST.
sdram_bist command will then be available in the BIOS:
litex> sdram_bist
sdram_bist <burst_length> <random>
litex> sdram_bist 256 0
Starting SDRAM BIST with burst_length=256 and random=0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 0 0
473 455 25 0
473 455 50 0
473 455 75 0
473 455 100 0
473 455 125 0
473 455 150 0
473 455 175 0
473 455 200 0
473 455 225 0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 250 0
473 455 275 0
473 455 300 0
473 455 325 0
473 455 350 0
473 455 375 0
473 455 400 0
473 455 425 0
473 455 450 0
473 455 475 0
WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS
473 455 500 0
473 455 525 0
473 455 550 0
473 455 575 0
473 455 600 0
473 455 625 0
litex>
|
2020-11-05 13:41:37 +01:00 |
Florent Kermarrec
|
97b35a0771
|
software/liblitedram/bist: update generator/checker control to configure end CSR.
|
2020-11-05 13:39:48 +01:00 |
Florent Kermarrec
|
3dffdbf628
|
build/xilinx: add missing \n on error reporting.
|
2020-11-04 11:32:25 +01:00 |
Florent Kermarrec
|
897b2ea412
|
boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command.
|
2020-11-04 11:15:04 +01:00 |
Florent Kermarrec
|
ffc554dede
|
soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents.
|
2020-11-04 10:58:16 +01:00 |
Florent Kermarrec
|
2c504783ca
|
bios/cmd/cmd_bios: add leds command to set leds value.
Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.
|
2020-11-04 10:22:14 +01:00 |
Florent Kermarrec
|
db836e8e5d
|
build: add toolchain check before running build script and improve error reporting.
|
2020-11-04 09:42:18 +01:00 |
bunnie
|
6e806ce60c
|
refactor SPI DOPI interface to support arbitrary commands, not jsut reads
lays the groundwork for doing page programming and sector erasing
|
2020-11-04 04:39:47 +08:00 |
Florent Kermarrec
|
f8cadc7b04
|
software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable).
|
2020-11-03 19:20:43 +01:00 |
enjoy-digital
|
b8d48385f6
|
Merge pull request #684 from sergachev/master
cores/cpu/zynq7000: fix axi hp slave registration
|
2020-11-03 14:53:10 +01:00 |
Florent Kermarrec
|
99b103998d
|
software/liblitedram: expose sdram_bist_loop.
|
2020-11-03 13:03:45 +01:00 |
Florent Kermarrec
|
9d94bcdef7
|
boards/platforms: cleanup pass to uniformize comments/separators/orders.
|
2020-11-03 10:59:12 +01:00 |
Florent Kermarrec
|
b63e2d3b94
|
boards/platforms: remove pcie_screamer (we'll add it to litex-boards).
|
2020-11-03 10:53:26 +01:00 |
Ilia Sergachev
|
cc652dda77
|
cores/cpu/zynq7000: fix axi hp slave registration
|
2020-11-03 00:55:16 +01:00 |
Florent Kermarrec
|
081d883421
|
targets/kc705: revert sys_clk_freq to 150MHz.
|
2020-11-02 19:52:28 +01:00 |
Florent Kermarrec
|
c1c095fdd4
|
targets/nexys_video: add SATA support.
|
2020-11-02 19:46:11 +01:00 |
Florent Kermarrec
|
cc95d89a6f
|
boards/kc705: update sata integration.
|
2020-11-02 19:01:10 +01:00 |
Florent Kermarrec
|
5b4e4a3b4a
|
CHANGES: update.
|
2020-10-30 15:41:36 +01:00 |
Florent Kermarrec
|
d18157edde
|
software/bios/cmd_litesata: add sata_init/sata_write commmands.
|
2020-10-30 15:38:45 +01:00 |
Florent Kermarrec
|
cb1badb173
|
software/liblitesata: add sata_write and update #ifdefs.
|
2020-10-30 15:38:17 +01:00 |
Florent Kermarrec
|
638d28d8d4
|
soc/sata: fix typo in Mem2Sector DMA.
|
2020-10-30 15:37:20 +01:00 |
Florent Kermarrec
|
060bbf1d59
|
soc/sata: add write support with LiteSATAMem2SectorDMA.
|
2020-10-30 12:20:12 +01:00 |
Florent Kermarrec
|
c4a6fe7d96
|
soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA).
|
2020-10-30 12:09:34 +01:00 |
Florent Kermarrec
|
7bcf8cb752
|
software/liblitedram: switch to uint32_t (as workaround for #322) and expose burst_length/random parameters to sdram_bist command.
|
2020-10-29 18:31:47 +01:00 |
Florent Kermarrec
|
07503d22ac
|
soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata).
|
2020-10-29 15:06:02 +01:00 |
Florent Kermarrec
|
b9ceed0f74
|
integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check.
|
2020-10-29 10:50:10 +01:00 |
Florent Kermarrec
|
e7ad705359
|
integration/soc: add initial SATA integration with DMA read support.
|
2020-10-29 10:15:46 +01:00 |
bunnie
|
e8c39ec3d2
|
add generic command processing state machine
facilitates page writes and sector erases
first commit, debugging now commencing
|
2020-10-29 05:09:18 +08:00 |
Florent Kermarrec
|
9b123f7c9a
|
software/liblitesata: implement sata_init with new CSR registers.
|
2020-10-28 19:55:19 +01:00 |
Florent Kermarrec
|
1fca7b9a91
|
software/liblitesata/sata_read: handle errors.
|
2020-10-28 18:59:36 +01:00 |
Florent Kermarrec
|
2bb46b305b
|
software/liblitesata: fix warning, typo, add TODO.
|
2020-10-27 09:39:01 +01:00 |
Florent Kermarrec
|
c0ba03ef66
|
targets/kc705: add initial SATA support.
|
2020-10-26 15:14:40 +01:00 |
Florent Kermarrec
|
4127af36b5
|
soc/software: add initial minimal LiteSATA support (allow booting from SATA drive).
|
2020-10-26 15:13:56 +01:00 |
bunnie
|
37f2ebe675
|
add responder for type 0 cti, so that wb debug access works
|
2020-10-25 17:50:56 +08:00 |
Florent Kermarrec
|
c474272f53
|
soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why.
|
2020-10-23 14:33:24 +02:00 |
Florent Kermarrec
|
e94876753d
|
soc/cores/icap: add back missing add_csr (was missing after adding add_reload method).
|
2020-10-23 08:00:43 +02:00 |
Florent Kermarrec
|
0dec446434
|
tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli.
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
|
2020-10-22 17:45:45 +02:00 |
Florent Kermarrec
|
30b226f895
|
soc/intergration/export: additional name override fix.
|
2020-10-22 08:55:14 +02:00 |
enjoy-digital
|
abdc8bb26e
|
Merge pull request #681 from Disasm/fix-svd-soc-name
Fix SoC name in SVD generator
|
2020-10-22 08:53:32 +02:00 |
Florent Kermarrec
|
4eb634ba2d
|
soc/interconnect/csr: fix CSRAccess values check.
|
2020-10-21 21:43:08 +02:00 |
enjoy-digital
|
e7b33a9ea8
|
Merge pull request #680 from daveshah1/dave/radiant-portname-fix
radiant: Use {} string for bus port names
|
2020-10-21 21:23:05 +02:00 |
enjoy-digital
|
7bbde6d05a
|
Merge pull request #679 from DurandA/patch-6
Add integer limits to stdint.h
|
2020-10-21 21:22:37 +02:00 |
Florent Kermarrec
|
c430587e91
|
soc/interconnect/stream/Shifter: add shift signal as optional parameter.
|
2020-10-21 15:52:53 +02:00 |
Vadim Kaushan
|
e4997295bd
|
Fix SoC name in SVD generator
The name was overwritten with one of the CSR region names
|
2020-10-21 16:40:35 +03:00 |
David Shah
|
66eb38cf84
|
radiant: Escape bus port names
Signed-off-by: David Shah <dave@ds0.me>
|
2020-10-21 14:05:33 +01:00 |
Florent Kermarrec
|
5a6b8f452d
|
soc/interconnect/stream: add Shifter.
Useful to shift stream data (ex for SerDes alignment).
|
2020-10-21 12:47:55 +02:00 |
Florent Kermarrec
|
ad04365e20
|
soc/cores/code_8b10b: add K helper.
|
2020-10-21 09:49:38 +02:00 |
Florent Kermarrec
|
e91ec2ed83
|
soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
With improvements to handle backpressure on non-continous streams.
|
2020-10-21 09:29:21 +02:00 |