The OpenC906 CPU core contains a RISC-V debug spec 0.13 compliant DM
with APB as its interface.
Add a CPU variant "debug" that will connect that APB to the main bus for
debugging.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
LiteX defaults to active-high reset signals, but OpenC906 uses
active-low ones, and the self.reset signal of openc906 module is wrongly
wired that it will force the CPU to run instead of force it to reset
(because it is ORed and then feed to the active-low reset line).
Fix this by using AND and inverting self.reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
- Update project description.
- Add plain text BSD 2-Clause License for Github detection.
- Add LiteX developers to copyrights (similar to README).
- Add "moral" conditions for use of the project.
The next move was to avoid use of soc_core_argdict and prefer use of soc_argdict directly,
so rename method now to avoid use on soc_core_argdict on targets/designs.
The LiteX OpenC906 core currently uses 0x0 as the base of main memory.
Hack to allow this when preloading a binary in litex_sim by adding a
command line argument.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Some builds may default to creating position independent executables
with a .dynamic section containing symbols that must be relocated at
runtime. This section appears after .data section and is included in
the output .bin, causing it to be included in the build time CRC
calculation. The runtime CRC calculation stops after .data, so there
was always a mismatch.
The litex bios has no support for relocating the dynamic symbols, so
disable pie on all platforms. This will improve compatibility with
distro toolchains.
Tested with:
marocchino / or1k-elf-gcc (GCC 12.1.0-2 Debian 1.0.3) 12.1.0
vexriscv / riscv64-linux-gnu-gcc (Debian 12.2.0-3) 12.2.0
microwatt / powerpc64le-linux-gnu-gcc (Debian 12.2.0-3) 12.2.0
Signed-off-by: Joel Stanley <joel@jms.id.au>
Currently we create a 32-bit Wishbone bus, connect LiteDRAM to it and
then connect it to the main SoC bus. This prevents us from getting
optimized performance from a wider main bus.
Make the intermediate bus to have the same width with the main bus.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Currently the code only supports 32/64 bit SoC data width.
Add support for any possible data width that is multiply of 32-bit.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
The default ethmac section address conflicts with main_ram defined for
openC906.
Add a custom position of ethmac to the memory map, which directly
follows the internal APB.
Also fix the start address of checked IO region from 0xa0000000 to
the full Region 1 in sysmap.h, and add plic and clint sections like
other RISC-V CPU cores (although they're internal to the CPU and won't
be usable by LiteX).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Florent Kermarrec
Mateusz Karlic
Icenowy Zheng
Gwenhael Goavec-Merou
Joel Stanley