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8778 Commits

Author SHA1 Message Date
Maciej Dudek 3c02323cfe liblitedram: discard singular 1s that are surrounded by 0s 
They are most likely glitches and won't be stable.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2023-01-26 13:12:25 +01:00
Maciej Dudek cd89b62ff6 liblitedram: Fix LFSR 
LFSR only returns 1 random bit per lfsr() call,
so we should concatenate 8 consecutive calls to obtain 1 random byte

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2023-01-26 13:12:25 +01:00
Maciej Dudek 48f547885a liblitedram: Correctly support single x4 IC 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2023-01-26 13:12:25 +01:00
Maciej Dudek 7b7fdadd26 liblitedram: Move pattern testing to its own function 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2023-01-26 13:12:25 +01:00
enjoy-digital 155bf31e04
Merge pull request #1581 from trabucayre/gowinpll_fix_warnings 
soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY
 2023-01-25 21:42:16 +01:00
Gwenhael Goavec-Merou 975cc9ecdc soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY 2023-01-25 20:47:30 +01:00
Florent Kermarrec 4b4fc7c6c0 cores/spi_flash: On Ultrascale: CS/DI/DO also need to be access through STARTUPE3, untested yet. 2023-01-25 12:19:10 +01:00
Florent Kermarrec cc91f2ee3a cores/spi_flash: Add USSPIFlash based on S7SPIFlash. 2023-01-25 10:31:40 +01:00
Dolu1990 03342065c3
Merge pull request #1571 from enjoy-digital/naxriscv-merge 
cpu/Vexriscv-smp fix silent generation failure
 2023-01-25 10:11:37 +01:00
enjoy-digital 04c240b847
Merge pull request #1579 from antmicro/msieron/fix-i2c 
I2C fixes
 2023-01-24 10:11:06 +01:00
enjoy-digital 92977eb359
Merge pull request #1580 from trabucayre/libbase_fix_with_cpp 
soc/software/libXX/YY.h: adding extern C (required to link with cpp code)
 2023-01-24 10:03:33 +01:00
Gwenhael Goavec-Merou 1eabc36c84 soc/software/libXX/YY.h: adding extern C (required to link with cpp code) 2023-01-24 07:05:05 +01:00
Michal Sieron 7f829f9e44 libbase/i2c: use busy_wait_us instead of cdelay 
`cdelay` function is not a proper thing to count time.
It wouldn't count SoC clocks, but CPU clocks.
But even then, there are multiple instructions in `cdelay`:
  - NOP
  - decrement
  - branch with compare
Assuming each instruction takes exactly 1 CPU cycle it is still wrong,
as we wait 3 time longer than requested.
But they don't take exactly 1 CPU cycle.
CPUs have caches, branch predictors, are out-of-order and so on.

So a much better way to count this time would be `busy_wait_us`.

I performed some test using vexriscv and Saleae Logic Analyzer:

vexriscv variant | requested I2C speed | actual (cdelay) | actual (busy_wait_us)
-----------------+---------------------+-----------------+----------------------
minimal          |  50 kHz             |  4 kHz          |  38 kHz
minimal          | 200 kHz             | 15 kHz          |  96 kHz
minimal          | 400 kHz             | 28 kHz          | 137 kHz
-----------------+---------------------+-----------------+----------------------
lite             |  50 kHz             | 12 kHz          |  40 kHz
lite             | 200 kHz             | 43 kHz          | 115 kHz
lite             | 400 kHz             | 74 kHz          | 180 kHz
-----------------+---------------------+-----------------+----------------------
standard         |  50 kHz             | 12 kHz          |  45 kHz
standard         | 200 kHz             | 48 kHz          | 159 kHz
standard         | 400 kHz             | 84 kHz          | 311 kHz

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-23 18:34:37 +01:00
Michal Sieron b122178876 libbase/i2c: don't enable pull-up after every bit 
Instead of enabling pull-up after every sent bit, enable it only after
sending all 8 bits.

This prevents some glitches from happening, where transition between
bits 0 to 0, produces a short spike.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-23 18:34:37 +01:00
Michal Sieron ac99709031 libbase/i2c: fix i2c_poll 
Change made in 1989d85 was supposed to poll I2C devices using both
writes and reads.

Here is a sequence that was supposed to happen:
  - I2C start
  - start I2C write
  - start I2C read
  - I2C stop

Unfortunately, the change worked differently:
  - I2C start
  - start I2C write
  - write byte of (slave_addr << 1 | 1)
  - I2C stop

This way, not only did the read not happen, but a potentially harmful
write was happening.

This commit makes it so following sequence takes place:
  - I2C start
  - start I2C write
  - if (I2C write returned NACK)
    - start I2C read
    - if (I2C read returned ACK)
      - read 1 byte and NACK it
  - I2C stop

An additional 1 byte read is happening, as some devices may be unable
to process I2C stop after initiating I2C read.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-23 18:33:51 +01:00
Michal Sieron b85705351c libbase/i2c: fix invalid return type 
This commit fixes invalid type warning in the `get_i2c_devs` function:
```
/some/path/litex/litex/soc/software/libbase/i2c.c: In function 'get_i2c_devs':
/some/path/litex/litex/soc/software/libbase/i2c.c:21:45: warning: returning 'struct i2c_dev (*)[1]' from a function with incompatible return type 'struct i2c_dev *' [-Wincompatible-pointer-types]
   21 | struct i2c_dev *get_i2c_devs(void) { return &i2c_devs; }
      |                                             ^~~~~~~~~
```

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-23 18:33:51 +01:00
Florent Kermarrec 5c922320a0 test/test_cpu: Disable NeoRV32 in CI (Seems to be broken with Verilator update). 2023-01-23 08:44:57 +01:00
Florent Kermarrec 556c8a7755 tools/litex_sim: Rename with-bist args to --with-sdram-bist. 2023-01-20 19:12:42 +01:00
enjoy-digital 13fcbca4dc
Merge pull request #1560 from antmicro/msieron/sdram-hw-test 
Add `sdram_hw_test` command
 2023-01-20 19:06:37 +01:00
enjoy-digital 406fd929e1
Merge pull request #1575 from antmicro/mdudek/fix_verilator_build 
Add missing package that caused verilator build to fail
 2023-01-20 19:02:28 +01:00
Florent Kermarrec 1610c643f9 cpu/vexriscv_smp/core: Take into account wishbone_force_32b No Direct Memory Bus error. 2023-01-20 13:36:06 +01:00
Michal Sieron fd59e8d55b liblitedram/bist: fix printf format warnings 
Use format constants for fixed width integer types to make it work on
both 32-bit and 64-bit CPUs without warnings.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-19 17:45:36 +01:00
Maciej Dudek 4552b8812b Add missing package that caused verilator build to fail 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2023-01-19 14:52:55 +01:00
enjoy-digital 73b88c6de1
Merge pull request #1574 from antmicro/msieron/fix-format-warnings 
liblitedram/utils: fix format warnings
 2023-01-19 12:42:40 +01:00
Florent Kermarrec f60e171b2f ci: Specify verilator sha1 (Build broken with recent versions). 2023-01-19 10:00:29 +01:00
Michal Sieron 89f60e66d3 liblitedram/utils: fix format warnings 
Use format constants for fixed width integer types to make it work on
both 32-bit and 64-bit CPUs without warnings.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-19 00:06:46 +01:00
Florent Kermarrec b9a0d1dbc3 soc/cores/prbs/PRBSChecker: Improve errors timings. 2023-01-18 15:47:10 +01:00
enjoy-digital dcb54b85a0
Merge pull request #1572 from gatecat/cva6_update 
cva6: Updating the core files
 2023-01-17 15:32:03 +01:00
gatecat b3e6bacc58 cva6: Updating the core files 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-17 14:50:36 +01:00
Dolu1990 92ef330c12 cpu/Vexriscv-smp fix silent generation failure 2023-01-16 18:02:32 +01:00
Florent Kermarrec 88453716dc cpu/vexriscv_smp/core: Only raise error with FPU. 2023-01-16 12:59:14 +01:00
Florent Kermarrec a4d5919a2a cpu/vexriscv_smp/core: Raise an error in do_finalize if no direct memory bus found and wishbone_memory is not set instead of forcing it. 
This could eventually be improved in the future but for now will prevent silent incorrect builds.
 2023-01-16 11:49:36 +01:00
Florent Kermarrec a39e2c836a tools/litex_sim: Fix missing update in ram_init. 2023-01-16 11:12:24 +01:00
Florent Kermarrec 5760c5ba1e integration/soc/alloc_region: Fix alignment of Origin on Size (Thanks @sensille). 2023-01-16 09:20:43 +01:00
enjoy-digital 8b14e64906
Merge pull request #1566 from antmicro/msieron/sdram-read-spd-fix 
liblitedram/sdram_spd: fix invalid buffer index
 2023-01-12 16:51:20 +01:00
Michal Sieron 6a38e83ff6 liblitedram/sdram_spd: fix invalid buffer index 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-12 13:48:33 +01:00
enjoy-digital 63169aa5db
Merge pull request #1564 from antmicro/msieron/fix-write-leveling-for-x4 
software/liblitedram: fix write leveling for x4 modules
 2023-01-12 12:49:32 +01:00
Florent Kermarrec f386f4a2a5 cores/pwm: Add reset signal to be able to synchronize PWM with an external signal. 2023-01-12 11:43:55 +01:00
Florent Kermarrec 461b48fbaa test/test_cpu: Disable microwatt test for now since seems broken (GHDL issue). 
Will need to be investigated:
https://github.com/enjoy-digital/litex/actions/runs/3900056883/jobs/6662146988

Command line:
ghdl --synth --out=verilog --std=08 --no-formal /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl -e microwatt_wrapper
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : elab-vhdl_annotations.adb:1401
Call stack traceback locations:
0x7fc79b8b0542 0x5631cf7cd3d0 0x5631cf7c8bf1 0x5631cf7c9219 0x5631cf7c93d2 0x5631cf7c977f 0x5631cf7ca0d3 0x5631cf7ca21a 0x5631cf7c9c41 0x5631cf7cbc0c 0x5631cf889270 0x5631cf97faf6 0x5631cf857fb0 0x5631cf988b5a 0x5631cf6d43d7 0x7fc79b432d8e 0x7fc79b432e3e 0x5631cf6d2f83 0xfffffffffffffffe
 2023-01-12 11:43:17 +01:00
enjoy-digital 803fb6323e
Merge pull request #1561 from roby2014/master 
Add Arch Linux setup support for RISC-V and OpenRISC toolchains
 2023-01-12 08:22:02 +01:00
awyxx fa28d70e62 added powerpc via AUR repository 2023-01-11 23:48:17 +00:00
Michal Sieron 881bdbbbef software/liblitedram: fix write leveling for x4 modules 
When using x4 modules, their response makes up only half a byte.
We need to extract the nibble and then test it.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:21:00 +01:00
enjoy-digital d67a7b13ae
Merge pull request #1563 from trabucayre/improve_LiteXArgumentParser 
Improve LiteXArgumentParser
 2023-01-11 19:15:58 +01:00
Gwenhael Goavec-Merou d70049c2e1 build/parser: adding a fallback to search for a platform explicitly into litex-boards package when platform name isn't found 2023-01-11 18:33:48 +01:00
Gwenhael Goavec-Merou 35f4913588 build/parser: adding a method to search default value for an argument into ArgParse._actions 2023-01-11 18:31:31 +01:00
awyxx 2f2a1e8947 Removed debug print 2023-01-10 21:42:49 +00:00
awyxx fec8bbe42c added arch linux support for riscv and openrisc toolchains 2023-01-10 21:41:35 +00:00
Michal Sieron cc27e3d6c7 cmds/cmd_litedram: add sdram_hw_test command 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:01:00 +01:00
Michal Sieron dbf030e4cf liblitedram/bist: add sdram_hw_test function 
It allows to perform a memtest (similar to `sdram_test`), but using DMAs
and bypassing system bus. This way, one can test ranges such above 4 GiB,
which was the limit with `sdram_test` due to address_width being limited
to 32 bits.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:01:00 +01:00
Michal Sieron e7e1b16027 liblitedram/bist: small refactor of bist functions 
`SDRAM_TEST_DATA_BYTES` definition was incorrect as it treated size
specified in CSR subregisters as if it was a byte count.

Correct way to calculate that is to use definitions from `sdram_phy.h`.

```
#define SDRAM_TEST_DATA_BYTES (SDRAM_PHY_DFI_DATABITS / 8 * SDRAM_PHY_PHASES)
```

Also:
- extracted code to `sdram_bist_[write|read]` functions
- made global variables static
- fixed formatting

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-10 13:00:54 +01:00