03e0f0d9a8
build/microsemi/libero_soc.py: replaced tabs by spaces
2024-05-30 08:57:59 +02:00
72cade55da
Applying updates for Libero SoC support ( #1855 )
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* Updated the new_project tcl function and removed set_device function.
* fixing tcl command set_root and adding in build_hierarchy command.
* Adding tcl command to export_prog_job file for FPExpress, saves in Libero SoC default location.
* Attempting error checking on Libero SoC installation, and typo clean up.
* Fixing -adv_options in new_project tcl command.
* Moving script_ext back to its original location.
* Commented out Libero environment variable.
* Removed Libero environment variable.
2024-05-30 08:56:27 +02:00
94e6bb0247
CHANGES.md: updated for eos_s3 and quicklogic f4pga toolchain
2024-05-30 08:46:42 +02:00
845e20c653
build/quicklogic/f4pga.py: fix Makefile, added a note for futur rework and link to toolchain install's instructions
2024-05-30 08:43:41 +02:00
5e0c3f0a04
tools/litex_json2dts_linux: add compatible, model
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Fixes these dt-schema validation errors:
/: 'compatible' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/: 'model' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
2024-05-30 16:18:11 +10:00
8a0d50b03e
tools/litex_json2dts_linux: add all soc sys_clk
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Adds clocks for a downstream iclink soc, for example
when builder.add_json() has imported soc clocks.
Node names are as per devicetree fixed-clock.yaml bindings.
2024-05-30 16:18:11 +10:00
ddc521b033
tools/litex_json2dts_linux: fix tlb-split
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This is also relevant to vexriscv_smp, not rocket specific.
Fixes these dt-schema validation errors:
cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-size'
from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-sets'
from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-size'
from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-sets'
from schema : http://devicetree.org/schemas/cpus.yaml#
2024-05-30 16:18:11 +10:00
d79c91daea
Merge pull request #1797 from Dasharo/s3_fix
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Change EOS S3 clock names
2024-05-30 06:24:14 +02:00
23e654db4c
Merge pull request #1968 from VOGL-electronic/fix_liblitespi
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liblitespi: Fix #1967
2024-05-28 15:43:07 +02:00
7a3b3dcfa2
Merge pull request #1966 from maass-hamburg/dts_zepyhr_include_cpu
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litex_json2dts_zephyr.py: include cpu
2024-05-28 15:42:38 +02:00
914167cb75
Merge pull request #1969 from enjoy-digital/ghdl_fix
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ci: Build/Install GHDL from sources.
2024-05-28 15:20:43 +02:00
5257ddaac0
ci: Build/Install GHDL from sources.
2024-05-28 14:33:05 +02:00
9165886525
snyc
2024-05-28 12:59:27 +02:00
025149c6c5
liblitespi: Fix #1967
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Make liblitespi independent from field_access_functions, since they were removed in 46911d5078
2024-05-28 11:27:02 +02:00
2dac84f32c
vexii l2 now support self flush. ex :
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--l2-self-flush=40c00000,40DD4C00,1666666
2024-05-27 17:37:30 +02:00
ae13f159c4
litex_json2dts_zephyr.py: include cpu
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include cpu, to share the clock-frequency with
zephyr.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-05-27 11:29:58 +02:00
47bab2fcff
CHANGES.md: Update.
2024-05-27 08:41:58 +02:00
2235c711e6
Merge pull request #1964 from acceleratedtech/jwise/output-load-trion
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efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion
2024-05-27 08:40:49 +02:00
aa9ad61674
Merge pull request #1962 from VOGL-electronic/master
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Add support for the Efinix reconfiguration interface
2024-05-27 08:36:40 +02:00
7ad3f2ce34
efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion
2024-05-24 18:10:24 -04:00
eed89ba3a3
Add support for the Efinix reconfiguration interface
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This adds low level support for the reconfiguration interface (sometimes also called remote update by Efinix)
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-05-24 08:50:58 +00:00
4a6efa47c1
Add variants to VexiiRiscv
2024-05-23 16:44:20 +02:00
56371c4d9f
Merge pull request #1961 from maass-hamburg/dts_zephyr_include_ctrl
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litex_json2dts_zephyr.py: include ctrl
2024-05-23 15:52:24 +02:00
77683f1659
litex_json2dts_zephyr.py: include ctrl
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include ctrl, needed to implement rebooting
in zephyr.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-05-22 16:16:03 +02:00
0af1ae8c64
soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the PSU's GPIO controler
2024-05-22 15:55:46 +02:00
44d049f3ad
litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required when this method is called more than once
2024-05-22 15:53:52 +02:00
14dbdeb0cb
soc/integration/export: Disable fields_access_function by default.
2024-05-21 10:26:18 +02:00
05030990b2
soc/integration/export: Add LITEX_CSR_ACCESS_FUNCTIONS/LITEX_CSR_FIELDS_ACCESS_FUNCTIONS defines to allow user to disable access functions.
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-DLITEX_CSR_ACCESS_FUNCTIONS=0 to disable CSR access functions.
-DLITEX_CSR_FIELDS_ACCESS_FUNCTIONS=0 to disable CSR access functions.
User can also avoid access function generation on get_csr_header call with:
- with_access_functions=False
- with_fields_access_functions=False
2024-05-21 10:26:13 +02:00
5b297f5601
soc/integration_export: Split C header generation by sections.
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- CSR Includes.
- CSR Registers/Fields Definition.
- CSR Registers Access Functions.
- CSR Registers Field Access Functions.
2024-05-21 10:26:08 +02:00
4502edd33e
soc/integration/export: Prepare split of C header generation in sections.
2024-05-21 10:26:04 +02:00
06bbbe78e4
vexii/naxii fix floating axi wires
2024-05-20 08:56:38 +02:00
21e0ec7f98
vexii/naxii fix floating axi wires
2024-05-20 08:55:05 +02:00
10083f4d87
Merge pull request #1958 from nrndda/patch-1
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Simple mistake fix
2024-05-18 21:33:25 +02:00
2d52c65613
Simple mistake fix
2024-05-18 19:09:13 +00:00
5eeb999694
update vexii
2024-05-18 16:59:27 +02:00
8c0f5447ed
fix nax/vexii git checkout process, thanks JoyBed
2024-05-18 10:01:29 +02:00
4b3f147fc8
CHANGES: Update.
2024-05-17 12:58:03 +02:00
d5f9d57c2b
Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart
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Zynqmp aximaster eth i2c uart
2024-05-17 12:54:06 +02:00
943c0c263d
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode
2024-05-17 11:02:41 +02:00
49488e5e01
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode
2024-05-17 11:02:31 +02:00
e95edaf9be
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii)
2024-05-17 11:02:16 +02:00
1986b79b9a
soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion
2024-05-17 11:02:02 +02:00
c5592ca8da
soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file
2024-05-17 11:01:46 +02:00
0720ffb404
Update vexii
2024-05-17 10:00:24 +02:00
882463d9db
Merge pull request #1955 from Dolu1990/nax64_irq
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cores/cpu/naxriscv: fix 64 bits IRQ support
2024-05-17 08:20:46 +02:00
122e060a5e
update vexii
2024-05-16 19:30:15 +02:00
74b300597b
cpu/naxriscv: fix 64 bits IRQ support
2024-05-16 18:59:40 +02:00
60b0273eda
Add baremetal IRQ support
2024-05-16 18:58:16 +02:00
57f74da8d8
Merge branch 'master' into vexiiriscv
2024-05-16 16:17:21 +02:00
d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs
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Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
2024-05-16 10:55:12 +02:00
Gwenhael Goavec-Merou
CLappin
Andrew Dennison
enjoy-digital
Dolu1990
Matthias Breithaupt
Fin Maaß
Joshua Wise
Dmitry