Commit Graph

816 Commits

Author SHA1 Message Date
Florent Kermarrec 5713ae381a actorlib/packet/Depacketizer: manage layouts without error signal 2015-07-22 21:43:21 +02:00
Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
Florent Kermarrec 71627cf9f0 bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant) 2015-06-19 08:37:16 +02:00
Florent Kermarrec f8b1152b98 wishbone: add Cache (from WB2LASMI) 2015-06-17 15:31:49 +02:00
Florent Kermarrec 33b536e505 migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter) 2015-06-02 19:29:38 +02:00
Florent Kermarrec 79624ce849 migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq fd16b66bdf genlib/cdc: add BusSynchronizer 2015-06-02 17:40:42 +08:00
Florent Kermarrec a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec 9cabcf14e9 migen/genlib/record: add leave_out parameter to connect
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00
Florent Kermarrec f6624b34f0 migen/actorlib/spi: apply missing CSR renaming 2015-05-13 10:17:31 +02:00
Florent Kermarrec 76302d7aa6 vpi: cleanup (thanks sb) 2015-05-13 10:13:14 +02:00
Florent Kermarrec 98cf103c65 vpi: fix and simplify windows simulation (ends of msg were ignored) 2015-05-13 03:03:34 +02:00
Florent Kermarrec 88a406ebec migen/genlib/misc: replace Timeout with WaitTimer from artiq 2015-05-12 16:14:58 +02:00
William D. Jones fe6eef7069 Windows simulation support 2015-05-09 21:09:52 +08:00
Alain Péteut 96bff77c36 add examples tests 2015-05-01 00:50:17 +08:00
Florent Kermarrec 1cbc468bda migen/actorlib/packet: add Packetizer and Depacketizer 2015-04-28 18:44:05 +02:00
Florent Kermarrec 0da9311d70 migen/genlib: avoid use of floating point in reverse_bytes 2015-04-27 21:04:18 +02:00
Florent Kermarrec 3ce5ff3722 migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer) 2015-04-27 15:14:38 +02:00
Florent Kermarrec f976b1916a migen/actorlib/misc: add BufferizeEndpoints
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
Florent Kermarrec e96ba1e46f migen/genlib/misc: add reverse_bytes 2015-04-27 15:08:10 +02:00
Florent Kermarrec 73a1687562 migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?) 2015-04-24 13:24:52 +02:00
Florent Kermarrec 67702f25ab migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
Florent Kermarrec bc30fc57e7 migen/fhdl: give explicit names to syntax specialization when asic_syntax is used 2015-04-24 12:14:14 +02:00
Florent Kermarrec 61c3efc5f5 migen/test: rename asic_syntax to test_syntax and simplify 2015-04-24 12:00:46 +02:00
Guy Hutchison 7ec0ecae11 test: add test for asic_syntax 2015-04-22 12:29:07 +08:00
Guy Hutchison 28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
Florent Kermarrec 3f15699964 revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
Florent Kermarrec d83e170872 global: more pep8
we will have to continue the work... volunteers are welcome :)
2015-04-13 21:33:44 +02:00
Florent Kermarrec f97d7ff44c global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
Florent Kermarrec 5f225c0475 global: pep8 (E225) 2015-04-13 21:11:13 +02:00
Florent Kermarrec 37ef9b6f3a global: pep8 (E231) 2015-04-13 20:50:03 +02:00
Florent Kermarrec 1051878f4c global: pep8 (E302) 2015-04-13 20:45:35 +02:00
Florent Kermarrec 17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Florent Kermarrec a2c17cdcef Merge branch 'master' of https://github.com/m-labs/migen 2015-04-13 09:37:03 +02:00
Sebastien Bourdeauducq c6904f9d63 sim: fix to support ConvOutput 2015-04-12 14:06:57 +08:00
Florent Kermarrec ff23960657 fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
Sebastien Bourdeauducq a69741b24e forgot other cordic files 2015-04-09 12:00:20 +08:00
Sebastien Bourdeauducq e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Sebastien Bourdeauducq 90c5512b25 genlib: remove cordic (will live in pdq2) 2015-04-08 11:35:53 +08:00
Robert Jordens 25e4d2a2db decorators: remove deprecated semantics 2015-04-05 18:47:45 +08:00
Robert Jordens 8798ee8d73 decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
Robert Jordens f26ad97624 decorators: fix ControlInserter 2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq db76defa2a fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00
Robert Jordens e702fb7727 decorators: fix class/instance logic 2015-04-04 19:16:58 +08:00
Robert Jordens 4091af69fd fhdl/decorators: make the transform logic more idiomatic
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
2015-04-04 19:16:50 +08:00
Florent Kermarrec ce0ff1e341 remove use of _r prefix on CSRs 2015-04-02 12:15:56 +02:00
Florent Kermarrec d67f24ddc7 migen/bank/description: remove support of _r prefix in CSRs 2015-04-02 12:13:22 +02:00
Sebastien Bourdeauducq c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
This reverts commit f03aa76292.
2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq dc88295338 Revert "migen/fhdl: pass fdict filename --> contents to specials"
This reverts commit ea04947519.
2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
This reverts commit 95cfc444e6.
2015-03-30 19:41:04 +08:00