503df5e93e
Add Diamond toolchain support for Linux.
...
This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
2017-07-20 13:21:10 +01:00
1885e50d54
Add Versa ECP5-5G Platform.
2017-07-05 15:01:07 +01:00
0894f9e6f7
targets: cleanup arty/nexys_video/kc705 and use better ddr3 timings on arty/nexys_video (found using the new bitslip/delay finder tool)
2017-07-04 09:01:29 +02:00
fe535db5ab
merge migen ee0e709 changes
2017-07-04 08:15:40 +02:00
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
bd876d4cd6
merge migen 9a6fdea3 changes
2017-06-28 22:47:13 +02:00
4d664730fe
soc/software/libbase: fix get_ident
2017-06-28 18:10:56 +02:00
e61d9eabc6
board/targets/sim: add identifier
2017-06-28 18:08:37 +02:00
4433e2449a
litex/build/sim: cleanup modules
2017-06-28 18:01:04 +02:00
c3710ec139
build/sim: cleanup serial2console and fix terminal mode
2017-06-28 17:38:09 +02:00
ebded4a1b9
README: add required packages for litex sim
2017-06-28 16:56:05 +02:00
5ece895fd3
litex/build/sim: add README
2017-06-28 16:55:32 +02:00
4a0a431119
litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex)
2017-06-28 16:28:45 +02:00
ab6f4de521
litex/build/sim: small cleanup
2017-06-28 16:25:56 +02:00
1d8298af94
litex/build/sim: add tapcfg submodule for ethernet
2017-06-28 16:18:15 +02:00
8510b12e93
litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept)
2017-06-28 16:14:13 +02:00
6631aa5385
boards/platforms/arty: add pmods
2017-06-23 10:50:37 +02:00
1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
bdc61106d1
README: consistency between projects
2017-06-22 17:01:13 +02:00
f720ef5631
soc/tools: simplify litex_server usage and integrage udp, pcie
2017-06-22 11:30:33 +02:00
41a91829eb
soc/tools: syntax fix on comm_pcie, import in __init__.py
2017-06-22 11:29:57 +02:00
c82c1d103f
soc/tools: fix debug prints of comm_pcie
2017-06-22 10:33:08 +02:00
684ae45dbe
soc/tools: remove csr builder from comm_udp (we should use litex_server)
2017-06-22 10:32:39 +02:00
4ea7026747
gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
2017-06-10 21:53:53 +02:00
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
157c2b17bc
boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port
2017-06-05 15:13:21 +02:00
a36986a501
gen/fhdl/verilog: list available clock domains on keyerror
2017-06-05 14:33:46 +02:00
931ea5ac75
gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise
...
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
2017-06-01 19:00:22 +02:00
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
ff2a9c2176
gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned)
2017-05-31 13:23:31 +02:00
4bc6cf6165
soc/cores: dna/xadc: add missing copyright
2017-05-16 21:18:32 +02:00
9350a7b5e6
soc/cores: add dna and xadc (for 7-series, add support for others fpgas?)
2017-05-16 21:02:33 +02:00
6a7604cbb0
Merge pull request #24 from mithro/vivado-mor1k-fix
...
vivado: Fix segfault with or1k.
2017-05-04 15:09:00 +02:00
5f9ff09c08
vivado: Fix segfault with or1k.
...
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
File "./make.py", line 82, in <module>
```
2017-04-29 16:44:18 +10:00
bedd428d9d
soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing.
2017-04-26 13:49:16 +02:00
bb582619eb
gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer
2017-04-25 15:13:47 +02:00
e0ce485a17
test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)
2017-04-25 10:57:34 +02:00
0daeff8689
gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)
2017-04-25 10:56:19 +02:00
456cce3ec6
gen/genlib/cdc: import gcd from math and not fractions (deprecated)
2017-04-25 10:55:13 +02:00
3ca0cb0cea
test: add test_gearbox skeleton
2017-04-24 21:41:46 +02:00
b4ebfb4031
test/test_targets: check top.v generation
2017-04-24 19:25:58 +02:00
4c7d460475
litex/gen/util/misc: import gcd from math and not fractions (deprecated)
2017-04-24 19:25:24 +02:00
35e3d93d9b
test: add basic test_targets.py
2017-04-24 19:13:17 +02:00
c0800d25a6
soc/integration/builder.py: don't take care of ROM when compile_software is forced to False
2017-04-24 19:12:30 +02:00
dc66dfcb55
test: add test_bitslip (initially in litedram)
2017-04-24 18:50:06 +02:00
Sergiusz Bazanski
Florent Kermarrec
Pierre-Olivier Vauboin
Tim 'mithro' Ansell