51592df260
debug
2023-09-14 07:19:05 +02:00
e2c3a50e99
core/naxriscv allow memory less gen
2023-09-13 23:10:10 +02:00
e8ed93c571
core/naxriscv git fix attempt
2023-09-13 20:41:27 +02:00
2e4ebc8ec3
core/naxriscv git fix attempt
2023-09-13 19:42:16 +02:00
b160507042
core/naxriscv add rvls git
2023-09-13 18:52:40 +02:00
50b9f44d26
make naxriscv dma optional again
2023-09-13 16:23:39 +02:00
d40d76fe4e
fix indent
2023-09-13 16:18:44 +02:00
5e0b8969ee
Provide a deployable naxriscv SMP
2023-09-13 16:16:27 +02:00
72447a1f49
Merge remote-tracking branch 'origin/master' into nax-smp
...
# Conflicts:
# litex/soc/cores/cpu/naxriscv/core.py
# litex/soc/integration/soc.py
2023-09-05 18:14:44 +02:00
943d652362
cores/naxriscv match axi width
2023-09-05 18:13:27 +02:00
99cb46fd3e
build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility
2023-09-05 16:44:47 +02:00
6c6cfeae7f
Merge pull request #1763 from josuah/radiant_wsl2
...
Allow use of Windows-side (.exe) Radiant toolchain
2023-09-03 19:27:32 +02:00
2e6ddd9dd9
build/lattice/radiant: allow use of Windows-side (.exe) radiant toolchain under WSL2
2023-09-02 22:28:40 +02:00
8853215033
Merge pull request #1762 from motec-research/dma_fix
...
proof of concept coherent dma fix
2023-09-02 08:22:40 +02:00
1bb4d299a6
vexrisc_smp: fix DMA bus address_width calculation
2023-09-02 11:46:11 +10:00
48ab96fd43
soc/intregation: fix cpu name in logging
...
Fixed CPU name being reported as irq name in logging.
```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
2023-09-02 11:46:11 +10:00
57faa9102f
CHANGES: Update.
2023-09-01 12:40:03 +02:00
f473261bc6
soc/dma_bus: Make SoCDMABusHandler use the Bus Standard of the DMA Bus defined in the CPU.
...
Also simplify code by using automatic Bus conversion of SoCBusHandler.
2023-09-01 12:19:11 +02:00
db2ad78860
interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it.
2023-09-01 12:16:15 +02:00
33efa09663
Merge pull request #1760 from motec-research/dts_linux_fix
...
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 10:46:04 +02:00
058cdd646b
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 16:54:41 +10:00
14012263af
Merge pull request #1758 from motec-research/spi_mmap_fix
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soc/cores/spi_mmap: Fix clock divider
2023-09-01 08:38:53 +02:00
d494e30166
soc/cores/spi_mmap: Fix clock divider
2023-09-01 12:34:51 +10:00
405296b7fd
interconnect/axi/axi_full: Fix missing switch to LiteXModule.
2023-08-31 19:36:21 +02:00
516038ce76
soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed)
2023-08-31 17:24:58 +02:00
fadf47d353
build/lattice/trellis: fix add_period_constraint signature (missing keep arg)
2023-08-31 16:52:48 +02:00
41357aba7d
xilinx/vivado: Fix issue with #1755 .
2023-08-31 16:38:50 +02:00
ad924a522a
interconnect/stream/AsyncFIFO: Remove Efinix workaround since seems to be solved with Efinity 2023.x.
2023-08-31 16:03:52 +02:00
124e0d22c9
Merge pull request #1755 from enjoy-digital/allows_clk_name_override
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build/xx/toolchains: allows override clock naming
2023-08-31 15:57:39 +02:00
46800176ae
build/xx/toolchains: allows override clock naming
2023-08-31 15:18:15 +02:00
2a7caa2696
build: all platforms: override add_period_constraint only when required
2023-08-31 12:29:09 +02:00
3f43481eb9
build/efinix/efinity: build_timing_constraints: set_false_path is unidirectional -> add another one to -> from_
2023-08-31 11:42:07 +02:00
a071cc343d
litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk only apply constraints on eth_rx_clk
2023-08-31 11:36:24 +02:00
9854c9f322
CHANGES: Update.
2023-08-30 18:11:11 +02:00
ff0df100e9
build/efinix: Add get_pin (from sig) to EfinixPlatform and use it to simplify/fix IOs exclusion.
2023-08-30 18:08:40 +02:00
72590dfde3
software/libliteeth: Fix udp_set_callback warning.
2023-08-30 17:44:00 +02:00
434e2225ea
software/liblitedram: Fix swap_bit warning.
2023-08-30 17:22:57 +02:00
c2714df198
build/efinix/common: Add initial EfinixDDROutput/EfinixDDRInput implementation.
...
Still need to figure out a few things:
- Clk is passed as a string for now.
- IOs exclusion still handled externally.
2023-08-30 11:28:48 +02:00
c0ab4ed1c1
build/io: Allow passing clk as str on DDRInput/Output, wrap DDROutput IOs and minor ident fixes.
2023-08-30 10:52:13 +02:00
6dff371835
build/efinix/common: Simplify IO exclusion in EfinixTristateImpl and fix corner cases (ex eth_mdio that was not automatically excluded).
2023-08-30 09:16:46 +02:00
9528f89d45
CHANGES: Update.
2023-08-29 17:15:45 +02:00
85dadb827a
clock/gowin_gw5a: Fix copyright.
2023-08-29 14:25:04 +02:00
c122fef5ac
Merge pull request #1741 from Icenowy/gw5apll
...
soc/cores/clock: initial GW5A support
2023-08-29 14:21:02 +02:00
1636c0ef8d
soc/cores/clock: initial GW5A support
...
GW5A has different PLLs than GW1N/GW2A, with multiple individual
ODIV's. GW5A-25 has a different PLL with GW5A[S]T-138, with lack of
dynamic control.
Add basic support for them.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-29 15:39:25 +08:00
a4498dcd03
nax dma wip, WARNING soc.py
2023-08-28 18:57:45 +02:00
82602f660c
interconnect/stream: Fix #1736 .
2023-08-28 16:19:31 +02:00
70e52b76fa
CHANGES: Update.
2023-08-28 16:04:43 +02:00
d29d2c09bb
interconnect/stream: Minor review/cleanup.
2023-08-28 16:02:52 +02:00
8efcc4fdea
Merge pull request #1736 from rowanG077/buf-endpoint-cfg
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soc/interconnect/stream: BufferizeEndpoints params
2023-08-28 15:58:46 +02:00
f7b35f09ae
build/efinix/efinity: don't hardcode efinity version, read from scripts/sw_version.txt
2023-08-28 14:43:17 +02:00
Dolu1990
Gwenhael Goavec-Merou
enjoy-digital
Josuah Demangeon
Andrew Dennison
Richard Tucker
Radek Pesina
Icenowy Zheng