Florent Kermarrec
552b0243b3
soc/interconnect/axi: remove dead code (thanks gsomlo)
2019-03-27 21:15:14 +01:00
enjoy-digital
b682dacdd7
Merge pull request #154 from daveshah1/yosys_xilinx_edif
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build/xilinx: Update Yosys write_edif parameters
2019-03-22 17:43:40 +01:00
David Shah
57e1ccd5f8
build/xilinx: Update Yosys write_edif parameters
2019-03-22 16:06:52 +00:00
Florent Kermarrec
fd7ed6c1ec
utils/litex_sim: fix main_ram_size
2019-03-16 21:25:02 +01:00
Florent Kermarrec
3f386dad7d
soc_core/get_mem_data: add json support
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example of json file:
{
"vmlinux.bin": "0x00000000",
"vmlinux.dtb": "0x01000000",
"initramdisk.gz": "0x01002000"
}
2019-03-16 21:23:36 +01:00
Florent Kermarrec
7bc13ba841
build/microsemi/libero_soc: add linux build script support
2019-03-16 09:33:16 +01:00
Florent Kermarrec
7b88980d06
vexriscv: allow user to use an external variant
2019-03-15 18:16:25 +01:00
Florent Kermarrec
b04a756abb
vexriscv/core: fix min variant
2019-03-15 17:49:39 +01:00
Florent Kermarrec
a549f0941b
utils/litex_sim: handle cpu_endianness for rom-init/ram-init
2019-03-13 10:56:09 +01:00
Florent Kermarrec
411bca790a
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified
2019-03-13 10:42:10 +01:00
enjoy-digital
7ec3ed4d89
Merge pull request #153 from railnova/fix_utils
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[fix] utils was omitted when installed from pip
2019-03-07 21:12:00 +01:00
chmousset
aed2e9b4b5
[fix] utils was not installed from pip
2019-03-07 09:40:58 +01:00
enjoy-digital
3543b56753
Merge pull request #152 from gsomlo/gls-trellis-svf
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build/lattice/trellis: generate bitstream directly in svf format
2019-03-06 23:41:20 +01:00
Gabriel L. Somlo
b014c7194b
build/lattice/trellis: also generate bitstream in svf format
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Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
2019-03-06 16:29:18 -05:00
Florent Kermarrec
317dba8314
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
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In the future, the PHYs should generated these constants.
2019-03-05 18:03:24 +01:00
Florent Kermarrec
7de1fe519a
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
2019-03-05 13:27:11 +01:00
Florent Kermarrec
ca63db4040
bios/sdram: use burstdet detection for ECP5DDRPHY init
2019-03-05 13:27:06 +01:00
enjoy-digital
2ebfab5e1f
Merge pull request #150 from daveshah1/trellis_bus_fixes
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lattice/common: Fix tristate buses with Trellis
2019-03-04 12:00:44 +01:00
David Shah
ebe8f600e1
lattice/common: Fix tristate buses with Trellis
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 10:50:56 +00:00
Florent Kermarrec
935f3a5337
boards/ulx3s: add device selection parameter
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ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
2019-03-04 09:40:14 +01:00
Florent Kermarrec
e6f97e08d2
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
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Now supported by Trellis/Nextpnr.
2019-03-04 09:27:31 +01:00
Florent Kermarrec
5ef28bdf75
build/lattice/trellis: add package support
2019-03-01 15:20:02 +01:00
Florent Kermarrec
1b34c07da9
build/lattice/trellis: basecfg now integrated in nextpnr
2019-03-01 14:20:00 +01:00
Florent Kermarrec
7e995eb418
boards/targets/ulx3s: allow building with diamond or trellis
2019-03-01 13:59:28 +01:00
Florent Kermarrec
4bf789eab9
soc/software/bios/boot: add vexriscv workaround
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Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
2019-03-01 09:16:48 +01:00
Florent Kermarrec
1fd81c2882
soc/integration: add initial SoCZynq SoC
2019-02-27 22:39:35 +01:00
Florent Kermarrec
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
Florent Kermarrec
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
Florent Kermarrec
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
Florent Kermarrec
6a4c133cd2
test: add basic test_csr
2019-02-27 21:46:00 +01:00
enjoy-digital
c9f9e237d9
Merge pull request #149 from daveshah1/versa_trellis
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Add trellis build option to versa_ecp5 and bring trellis support up to date
2019-02-25 19:26:07 +01:00
David Shah
ff7e0fab6a
versa_ecp5: Add option to build with Trellis
2019-02-25 18:02:04 +00:00
David Shah
024b41c5b2
trellis: Add LPF frequency constraints and remove -nomux
2019-02-25 18:01:35 +00:00
Florent Kermarrec
e38dfd99e8
soc/software/sdram: fix compilation on ultrascale
2019-02-25 16:12:21 +01:00
Florent Kermarrec
5f29a12ee7
targets/versa_ecp5: integrate DDR3
2019-02-25 15:27:08 +01:00
Florent Kermarrec
3dd529e40b
soc/software/bios/sdram: add ECP5 support
2019-02-25 14:41:33 +01:00
Florent Kermarrec
2fd6d0e7e1
soc/software/bios/sdram: improve write_level robustness
2019-02-25 14:38:24 +01:00
Florent Kermarrec
36772b75f6
soc/software/bios/sdram: improve sdrlevel readibility
2019-02-25 14:37:31 +01:00
Florent Kermarrec
6a980781d3
soc/software/bios/sdram: add helpers for rst/inc of delays
2019-02-25 14:36:47 +01:00
enjoy-digital
dad7b292aa
Merge pull request #148 from daveshah1/versa_remove_n
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versa_ecp5: Remove negative diff IO pins
2019-02-22 14:32:45 +01:00
David Shah
321dd8fcf6
versa_ecp5: Remove negative diff IO pins
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In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
2019-02-22 12:12:10 +00:00
Florent Kermarrec
c03b1ad13a
platforms/versa_ecp5: add ddram pins
2019-02-20 22:45:19 +01:00
Florent Kermarrec
ff155a474d
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
2019-02-16 00:08:24 +01:00
Florent Kermarrec
d3ecdd9995
soc/cores/clock: add actual clk_freqs to config
2019-02-14 10:41:27 +01:00
Florent Kermarrec
af52842fbb
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
2019-02-12 12:12:40 +01:00
Florent Kermarrec
32543430c0
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
2019-02-11 19:41:12 +01:00
Florent Kermarrec
aabf042d38
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
2019-02-11 09:23:39 +01:00
Florent Kermarrec
f51ad43607
build/lattice/common: add LatticeiCE40DDROutput
2019-02-07 16:23:55 +01:00
Florent Kermarrec
22ccf9ddf1
platforms/nexys_video: add LPC transceivers pins
2019-02-01 23:39:17 +01:00
Florent Kermarrec
1d9c55888f
build/sim: add jtagremote module (thanks LamdaConcept)
2019-01-30 14:01:19 +01:00
