Florent Kermarrec
55d9b3a403
soc/add_sdram: Introduce data_width_ratio and fix id_width in UpConvert case.
2022-02-18 11:34:08 +01:00
Florent Kermarrec
51d952c2d3
interconnect/axi: Simplify/Fix AXIUpConverter.
...
Assume size of "axi_from" burst >= "axi_to" data_width.
2022-02-18 11:33:28 +01:00
Florent Kermarrec
8dbb572b7a
cpu/naxriscv: Prepare for data_width conversion in LiteX (not yet enabled).
2022-02-17 18:36:42 +01:00
Florent Kermarrec
6788f3b9cb
cpu/naxriscv/core: Uncomment git_setup and update sha1.
2022-02-17 17:51:40 +01:00
enjoy-digital
52ed20178c
Merge pull request #1213 from Dolu1990/naxriscv
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cpu/naxriscv Add pythondata support
2022-02-17 17:32:00 +01:00
Florent Kermarrec
1052584cf7
integration/soc/add_sdram: Use new AXIUpConverter when up-converting is required (Instead of going through Wishbone).
2022-02-17 17:23:16 +01:00
Florent Kermarrec
ea49be9302
interconnect/axi: Add initial AXIUpConverter (for use with NaxRiscv/LiteDRAM).
2022-02-17 17:22:30 +01:00
Florent Kermarrec
f62eca77e3
test/test_axi: Minor cleanups.
2022-02-17 15:13:05 +01:00
Dolu1990
a3243e32ec
cpu/naxriscv Add pythondata support
2022-02-17 14:59:56 +01:00
Florent Kermarrec
d0dc5c8d95
CHANGES: Update.
2022-02-17 10:36:05 +01:00
Florent Kermarrec
c494ea231b
cpu: Add initial NaxRiscv support (From out of tree prototyping in litex_naxriscv_test).
...
- Supporting rv32ima for now.
- No interrupt support yet.
- AXI4 direct interfaces to LiteDRAM (fixed at 128-bit for now).
- AXI4-Lite interfaces to LiteX main bus.
- Pre-generated netlist used for now (need to allow customization/re-generation).
- Running in simulation with: litex_sim --cpu-type=naxriscv
- Running on hardware with: python3 -m litex_boards.targets.digilent_arty --cpu-type=naxriscv --build --load
Demo with Linux and Doom on SDS1104X-E scope:
https://twitter.com/enjoy_digital/status/1493996880593887235
2022-02-17 10:28:48 +01:00
Florent Kermarrec
38a047bed1
cpu: Add initial NEORV32 support (From out of tree prototyping in litex_neorv32_test repo).
...
- Only configured for rv32i for now (need to create variants).
- I/DBus interfaces probably not optimal (latency).
- Converted from VHDL to Verilog through GHDL-Yosys-Synth (should also support direct VHDL use with toolchains supporting it).
- Interrupt not yet implemented.
- Running in simulation with litex_sim --cpu-type=neorv32.
- Running on Arty with: python3 -m litex_boards.targets.digilent_arty --cpu-type=neorv32 --build --load:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 14 2022 16:10:24
BIOS CRC passed (83edf3c3)
Migen git sha1: ac70301
LiteX git sha1: 0d218306
--=============== SoC ==================--
CPU: NEORV32 @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 800MT/s (CL-7 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |11000000000000000000000000000000| delays: 01+-01
m0, b02: |00011111111111111000000000000000| delays: 10+-07
m0, b03: |00000000000000000000111111111111| delays: 26+-06
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b02 delays: 10+-07
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |10000000000000000000000000000000| delays: 00+-00
m1, b02: |00111111111111111000000000000000| delays: 09+-07
m1, b03: |00000000000000000001111111111111| delays: 25+-06
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
best: m1, b02 delays: 09+-07
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 9.3MiB/s
Read speed: 13.2MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2022-02-17 09:59:30 +01:00
Florent Kermarrec
d37ef60e70
remote/comm_udp: Increase timeout.
2022-02-16 17:57:24 +01:00
Florent Kermarrec
edf65107fb
libliteeth/tftp: Implement blocksize support (RFC2348) and increase blocksize from 512 bytes to 1024 bytes (mechanically increase filesize limitation from 32MB to 64MB).
...
See https://datatracker.ietf.org/doc/html/rfc2348 .
2022-02-16 16:46:26 +01:00
Florent Kermarrec
f46d1c190b
cpu/integration: Fix csr_decode.
2022-02-15 22:17:45 +01:00
enjoy-digital
9f2ffbb7ef
Merge pull request #1208 from trabucayre/cpu_fix_csr_decoding
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Cpu fix csr decoding
2022-02-15 22:05:51 +01:00
Florent Kermarrec
855bc26f16
litex_setup/cv32e41p: Only install it with full config.
2022-02-15 09:45:23 +01:00
enjoy-digital
2993928b31
Merge pull request #1207 from pcotret/cv32e41p_support
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Add support for the CV32E41P RISC-V CPU
2022-02-15 09:43:03 +01:00
enjoy-digital
de6238e7c0
Merge pull request #1201 from shenki/microwatt-countzero
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microwatt: Move to latest and add countzero module
2022-02-15 09:36:43 +01:00
Gwenhael Goavec-Merou
0427006663
soc/cores/cpu: eos, zynq7000 & zynqmp: don't decode CSR address
2022-02-15 07:32:26 +01:00
Gwenhael Goavec-Merou
af69c572d8
litex/soc/integration/soc: SocRegion: allows to bypass decoding; SoC: add attribute to bypass CSR decoding
2022-02-15 07:31:19 +01:00
Pascal Cotret
d4448827ac
add cv32e41p
2022-02-14 22:43:34 +01:00
Pascal Cotret
d506b4418e
add isr support for cv32e41p
2022-02-14 22:09:46 +01:00
Pascal Cotret
86373605ce
add pythondata for cv32e41p
2022-02-14 22:06:25 +01:00
Florent Kermarrec
0d2183062d
cpu/serv: Remove duplicated separator.
2022-02-14 11:52:29 +01:00
Florent Kermarrec
f91941731a
build/xilinx/platform: Add specialized add_platform_command to handle yosys+nextpnr specificities.
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Also remove symbiflow+nextpnr commented flow.
2022-02-14 10:44:13 +01:00
Florent Kermarrec
378c430dd0
soc/add_sdram: Fix typo when removing Rocket specific hardcoding.
2022-02-12 21:47:08 +01:00
Florent Kermarrec
dff33885de
cpu/zynqmp: Use dict for fpd/lpd selection.
2022-02-09 16:03:53 +01:00
enjoy-digital
80fd8e26a7
Merge pull request #1203 from trabucayre/zynqmp_complete_axi
...
zynqmp/core: allows users to select data_size and interface id
2022-02-09 15:46:46 +01:00
Gwenhael Goavec-Merou
b0d9223b78
zynqmp/core: allows users to select data_size and interface id
2022-02-09 07:03:44 +01:00
Florent Kermarrec
ad78965f41
soc/add_sdram/axi: Avoid some Rocket specific hardcoding (to use it on other CPUs).
2022-02-08 18:30:55 +01:00
Florent Kermarrec
7cc781f7be
cpu/zynq7000: Add Ilia to copyrights.
2022-02-07 07:57:59 +01:00
Florent Kermarrec
b749b3acb7
cpu/zynqmp: Add missing header/copyrights.
2022-02-07 07:57:29 +01:00
enjoy-digital
bd3d063d87
Merge pull request #1199 from sergachev/feature/zynqmp
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cores/cpu: add ZynqMP (UltraScale+ MPSoC) support
2022-02-07 07:53:25 +01:00
Joel Stanley
420934e206
microwatt: Move to latest and add countzero module
...
Mcrowatt has renamed countbits to countzero. Update to the latest and
update the file list.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-07 12:22:11 +10:30
Ilia Sergachev
5aee6359e6
cores/cpu: add ZynqMP (UltraScale+ MPSoC) support
2022-02-06 13:50:48 +01:00
Florent Kermarrec
55a790308f
cores/bitbang: Add TODO.
2022-02-04 09:01:00 +01:00
enjoy-digital
8dd2940bd0
Merge pull request #1197 from fjullien/align_vtg_hsync_vsync
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video: align hsync and vsync generated by the vtg
2022-02-04 08:32:46 +01:00
Franck Jullien
25152fe4de
video: align hsync and vsync generated by the vtg
2022-02-03 14:26:50 +01:00
Florent Kermarrec
26c44af3f7
cores/bitbang: Simplify HAS_I2C by doing it directly in collect_i2c_info.
2022-02-03 11:34:40 +01:00
enjoy-digital
8f5d971491
Merge pull request #1196 from fjullien/fix_efinix_tri_state
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efinix: fix EfinixTristateImpl
2022-02-03 11:13:11 +01:00
enjoy-digital
ef0c2043f1
Merge pull request #1195 from fjullien/i2c_multi_devices
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i2c: handle multiple i2c controllers in the BIOS
2022-02-03 11:12:57 +01:00
Franck Jullien
5cc08dfa64
i2c: handle multiple i2c controllers in the BIOS
...
A new command is introduced: "i2c_dev".
With this command you can list i2c devices and choose on to be active.
2022-02-03 09:27:10 +01:00
Florent Kermarrec
9413f5dc14
cores/bitbang: Fix typos in init changes.
2022-02-02 15:35:06 +01:00
Florent Kermarrec
8baf5cacc1
CHANGES: Update.
2022-02-02 12:05:46 +01:00
Florent Kermarrec
7ed448cd52
cores/bitbang: Attach I2C init table directly to I2C cores and avoid global add_i2c_init_table SoC method.
2022-02-02 10:57:50 +01:00
enjoy-digital
732529ecdf
Merge pull request #1193 from fjullien/i2c_master_init_values
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i2c: automatic device init by the BIOS
2022-02-02 09:59:31 +01:00
Franck Jullien
7a714c74af
i2c: automatic device init by the BIOS
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The BIOS can now initialize I2C peripherals during the boot.
The add_i2c_init_table method of the soc speficy parameters:
self.submodules.i2c = I2CMaster(pads)
self.add_i2c_init_table("i2c", i2c_addr=0x4c, table=it6263_i2c_hdmi_tx)
it6263_i2c_hdmi_tx = [
(0x05, 0x40),
(0x04, 0x3D),
(0x04, 0x1D)
...
The table is a list of tupple as (address, value).
2022-02-01 21:22:51 +01:00
Franck Jullien
be8e825a0b
efinix: fix EfinixTristateImpl
2022-02-01 21:14:35 +01:00
Florent Kermarrec
78ecf50ad5
cores/jtag: Make primitive selection more flexible (and simplify new devices support).
2022-02-01 12:44:18 +01:00