Commit Graph

9164 Commits

Author SHA1 Message Date
Florent Kermarrec 04a33c5ddb CHANGES: Update. 2023-09-18 09:09:45 +02:00
enjoy-digital 4639c7b39c
Merge pull request #1776 from Dolu1990/nax-smp
core/naxriscv provide a deployable NaxRiscv SMP
2023-09-18 09:05:43 +02:00
Florent Kermarrec 8bd548d453 CHANGES.md: Start listing changes since 2023.08. 2023-09-18 09:02:05 +02:00
Florent Kermarrec 46d9d8c780 README: Update sponsors. 2023-09-18 09:02:00 +02:00
Florent Kermarrec b931499c12 build: Remove osfpga skeleton (would need feedbacks & updates). 2023-09-18 09:01:48 +02:00
enjoy-digital 351a583f1c
Merge pull request #1780 from timkpaine/tkp/version
update version number to 2023.08
2023-09-18 08:37:57 +02:00
Tim Paine 6162a6dc90 update version number to 2023.08 2023-09-17 17:42:53 -04:00
Florent Kermarrec de608ee114 ci: Switch install to --dev. 2023-09-17 21:59:55 +02:00
Giulio Girardi eb54ec7402 Add Debug support for NEORV32 2023-09-16 10:41:18 +00:00
enjoy-digital 639462ce46
Merge pull request #1778 from zeldin/issue_1777
gen/fhdl/verilog: Fix #1777.
2023-09-15 13:21:38 +02:00
Marcus Comstedt 6da1482336 gen/fhdl/verilog: Fix #1777. 2023-09-14 17:53:51 +02:00
Dolu1990 ff3318b20d
Update litex_setup.py with naxriscv smp 2023-09-14 11:25:02 +02:00
Florent Kermarrec a2c2c211c5 Changes.md: Release 2023.08. 2023-09-14 10:47:37 +02:00
Dolu1990 51592df260 debug 2023-09-14 07:19:05 +02:00
Dolu1990 e2c3a50e99 core/naxriscv allow memory less gen 2023-09-13 23:10:10 +02:00
Dolu1990 e8ed93c571 core/naxriscv git fix attempt 2023-09-13 20:41:27 +02:00
Dolu1990 2e4ebc8ec3 core/naxriscv git fix attempt 2023-09-13 19:42:16 +02:00
Dolu1990 b160507042 core/naxriscv add rvls git 2023-09-13 18:52:40 +02:00
Dolu1990 50b9f44d26 make naxriscv dma optional again 2023-09-13 16:23:39 +02:00
Dolu1990 d40d76fe4e fix indent 2023-09-13 16:18:44 +02:00
Dolu1990 5e0b8969ee Provide a deployable naxriscv SMP 2023-09-13 16:16:27 +02:00
Dolu1990 c16add73b4 core/vexriscv_smp add --expose-time, which add "clint_time" as output of the cpu. 2023-09-12 10:42:44 +02:00
Dolu1990 5d9dd1059d core/usb_ohci fix generation 2023-09-12 10:41:47 +02:00
Florent Kermarrec d165418719 CHANGES.md: Update. 2023-09-12 09:35:53 +02:00
Florent Kermarrec bcc7e56dc6 build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code. 2023-09-12 09:30:45 +02:00
Florent Kermarrec 412f0f59b9 build/io: Add ClkInput/Ouptut to be able to abstract Clk Input/Output primitives. 2023-09-12 09:29:45 +02:00
Florent Kermarrec 36ce71d59b clock/efinix: Avoid manual n parameter and handle it internally. 2023-09-11 10:11:58 +02:00
Dolu1990 112f78bde3 cores/vexriscv_smp add risc-v official debug support via --with-privileged-debug
Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
2023-09-08 16:42:09 +02:00
Florent Kermarrec 022bdf3cdc tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers. 2023-09-08 16:12:04 +02:00
Florent Kermarrec 6c30cb8695 litex_setup.py: Use fixed sha1 version of Migen.
Migen switched from setup.py to pyproject.toml, we'll need to handle this.
2023-09-08 10:41:30 +02:00
Florent Kermarrec fbae6e8e37 CHANGES.md: Update. 2023-09-07 14:27:12 +02:00
enjoy-digital e1025c610a
Merge pull request #1769 from Icenowy/gw5a-pll-fix
clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
2023-09-06 09:15:42 +02:00
enjoy-digital e185871267
Merge pull request #1767 from josuah/fix_radiant_platform_detection
build/lattice/radiant: fix uname() not prefixed by 'os.'
2023-09-06 09:15:01 +02:00
Dolu1990 72447a1f49 Merge remote-tracking branch 'origin/master' into nax-smp
# Conflicts:
#	litex/soc/cores/cpu/naxriscv/core.py
#	litex/soc/integration/soc.py
2023-09-05 18:14:44 +02:00
Dolu1990 943d652362 cores/naxriscv match axi width 2023-09-05 18:13:27 +02:00
Gwenhael Goavec-Merou 99cb46fd3e build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility 2023-09-05 16:44:47 +02:00
Icenowy Zheng 7afe06a60c clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
When targeting GW5A-25 ES, the Gowin IDE has a more strict frequency
range.

Change the range when GW5A- is matched to this.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-09-05 16:50:49 +08:00
Josuah Demangeon 5e4628f1fe build/lattice/radiant: fix uname() not prefixed by 'os.' 2023-09-04 19:30:29 +02:00
enjoy-digital 6c6cfeae7f
Merge pull request #1763 from josuah/radiant_wsl2
Allow use of Windows-side (.exe) Radiant toolchain
2023-09-03 19:27:32 +02:00
Josuah Demangeon 2e6ddd9dd9 build/lattice/radiant: allow use of Windows-side (.exe) radiant toolchain under WSL2 2023-09-02 22:28:40 +02:00
Dolu1990 8853215033
Merge pull request #1762 from motec-research/dma_fix
proof of concept coherent dma fix
2023-09-02 08:22:40 +02:00
Andrew Dennison 1bb4d299a6 vexrisc_smp: fix DMA bus address_width calculation 2023-09-02 11:46:11 +10:00
Andrew Dennison 48ab96fd43 soc/intregation: fix cpu name in logging
Fixed CPU name being reported as irq name in logging.

```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
2023-09-02 11:46:11 +10:00
Florent Kermarrec 57faa9102f CHANGES: Update. 2023-09-01 12:40:03 +02:00
Florent Kermarrec f473261bc6 soc/dma_bus: Make SoCDMABusHandler use the Bus Standard of the DMA Bus defined in the CPU.
Also simplify code by using automatic Bus conversion of SoCBusHandler.
2023-09-01 12:19:11 +02:00
Florent Kermarrec db2ad78860 interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it. 2023-09-01 12:16:15 +02:00
enjoy-digital 33efa09663
Merge pull request #1760 from motec-research/dts_linux_fix
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 10:46:04 +02:00
Richard Tucker 058cdd646b tools/litex_json2dts_linux: fix missed sdcard_ references 2023-09-01 16:54:41 +10:00
enjoy-digital 14012263af
Merge pull request #1758 from motec-research/spi_mmap_fix
soc/cores/spi_mmap: Fix clock divider
2023-09-01 08:38:53 +02:00
Radek Pesina d494e30166 soc/cores/spi_mmap: Fix clock divider 2023-09-01 12:34:51 +10:00