Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,164 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

9164 Commits

Author SHA1 Message Date
Florent Kermarrec e6d950bcb0 gen/fhdl/verilog: Add module hierarchy generation after module definition. 
Will give a better overview of the generated verilog and will also ease comparing changes/track regressions.
 2023-11-03 11:08:40 +01:00
Florent Kermarrec 4a1486b1db gen/fhdl/hierarchy: Add with_colors parameters to allow enabling/disabling colors. 2023-11-03 11:06:41 +01:00
Florent Kermarrec 4497569118 gen/context: Rename soc to top. 2023-11-03 11:05:57 +01:00
Florent Kermarrec 27c55999c6 gen/common/colorer: Add enable parameter to allow enabling/disabling coloring. 2023-11-03 11:05:09 +01:00
Florent Kermarrec 1f200c83f3 build: Minor cleanups on get_verilog calls. 2023-11-03 11:04:31 +01:00
Florent Kermarrec b60bd92533 gen/fhdl/verilog: Rename _print_xy to _generate_xy and cleanup imports. 2023-11-03 10:14:38 +01:00
enjoy-digital 71ae8fe828
Merge pull request #1824 from trabucayre/add_64_bus_support_v2 
soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor
 2023-10-31 21:17:31 +01:00
Gwenhael Goavec-Merou 755808e287 soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor 2023-10-31 11:59:49 +01:00
Florent Kermarrec 9b8a5b6385 CHANGES: Update. 2023-10-30 19:40:42 +01:00
enjoy-digital 8c73afea91
Merge pull request #1823 from trabucayre/cpuNone_config 
litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width
 2023-10-30 18:42:54 +01:00
Gwenhael Goavec-Merou 16133359d6 soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width) 2023-10-30 18:13:46 +01:00
Gwenhael Goavec-Merou eedebd8adb litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width 2023-10-30 17:17:16 +01:00
enjoy-digital 4b9601bdab
Merge pull request #1822 from trabucayre/rework_tools 
tools: litex_server, litex_client and remote: don't hardcode bus address
 2023-10-30 17:13:46 +01:00
Gwenhael Goavec-Merou a2c39a7bbf tools: litex_server, litex_client and remote: don't hardcode bus address 2023-10-30 16:20:31 +01:00
enjoy-digital 5efdbd9c20
Merge pull request #1821 from trabucayre/uartbone_add_width 
UARTBone addr width
 2023-10-30 15:03:37 +01:00
Gwenhael Goavec-Merou 321254cc38 soc/integration/soc: pass bus.address_width to UARTBone constructor 2023-10-30 11:14:30 +01:00
Gwenhael Goavec-Merou f06ef5205a soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor 2023-10-30 11:13:40 +01:00
Gwenhael Goavec-Merou 9374196974 soc/cores/uart: allows 64bits in Stream2Wishbone 2023-10-30 11:03:16 +01:00
Florent Kermarrec b5a9106f56 cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame. 2023-10-27 18:09:03 +02:00
enjoy-digital 5842ad7d14
Merge pull request #1818 from Dolu1990/nax-smp 
core/naxriscv update to main branch
 2023-10-27 16:32:28 +02:00
Dolu1990 5e482d641c core/naxriscv switch to main branch, and implement a reset controller internaly 2023-10-27 16:06:07 +02:00
Florent Kermarrec d021564fca interconnect/wishbone: Revert SRAM to Module, needs to be investigated. 2023-10-27 15:24:57 +02:00
enjoy-digital ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue 
test_csr: test cases to demonstrate a CSRStatus() issue
 2023-10-27 12:52:25 +02:00
Florent Kermarrec c44b906d9f interconnect/stream: Revert Convert to Module, needs to be investigated. 2023-10-27 12:33:37 +02:00
Florent Kermarrec 856d7452b3 gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains. 2023-10-27 12:26:54 +02:00
Florent Kermarrec fa629b782f CHANGES: Update. 2023-10-27 11:40:31 +02:00
enjoy-digital e55cf0f6d9
Merge pull request #1804 from zeldin/ecp5_pll_phase 
cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
 2023-10-27 11:37:50 +02:00
Florent Kermarrec 63159aa187 soc/cores: Minor cosmetic changes. 2023-10-27 11:29:38 +02:00
Florent Kermarrec 48f27707d1 soc/cores: Make sure all Modules are switched to LiteXModule. 2023-10-27 11:16:55 +02:00
Florent Kermarrec a2820cba96 interconnect/packet: Switch to LiteXModule. 2023-10-27 11:07:31 +02:00
Florent Kermarrec fa521f5c89 interconnect/wishbone: Switch to LiteXModule. 2023-10-27 11:05:37 +02:00
Florent Kermarrec 9ccac7f7e0 interconnect/stream: Switch to LiteXModule. 2023-10-27 11:03:33 +02:00
Florent Kermarrec 002aad7a43 soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls. 2023-10-27 10:55:13 +02:00
enjoy-digital cd3265b16c
Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addressing 
Add wishbone word/byte addressing.
 2023-10-27 10:12:28 +02:00
Andrew Dennison 203726bc03 test_csr: test cases for issue 
'status' reads as 0 in simulation when CSRStatus has fields.
 2023-10-27 13:05:51 +11:00
Florent Kermarrec 6e928efe82 cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting. 2023-10-26 17:50:39 +02:00
Florent Kermarrec 75752b4bff cores/cpu: Make data_width/address_width/addressing explicit for all Wishbone interfaces. 2023-10-26 17:40:16 +02:00
Florent Kermarrec 7dc11e586b soc/add_adapter: Add initial addressing conversion between byte/word addressed. 2023-10-26 17:25:30 +02:00
Florent Kermarrec b19b7ed001 axi/axi_lite_to_wishbone: Add different address shift when Wishbone is byte/word addressed. 2023-10-26 17:24:37 +02:00
Florent Kermarrec dde9605a5d csr_bus: Add addressing property. 2023-10-26 17:23:31 +02:00
Florent Kermarrec c5d869447a ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed. 2023-10-26 17:23:12 +02:00
Florent Kermarrec 4524262f64 axi/axi_lite: Add addressing parameters and assert on byte. 
Useful to have similar properties than Wishbone.
 2023-10-26 17:18:38 +02:00
Florent Kermarrec d6f7652b68 axi/axi_full: Add addressing parameters and assert on byte. 
Useful to have similar properties than Wishbone.
 2023-10-26 17:18:23 +02:00
Florent Kermarrec a4539c3dae interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing). 2023-10-26 17:16:59 +02:00
enjoy-digital 7006b49a39
Merge pull request #1812 from trabucayre/efinix_ti60f100_spiflash 
build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support
 2023-10-25 17:47:28 +02:00
Gwenhael Goavec-Merou ba2913f137 build/efinix/ifacewriter: adding internal Ti60F100 SPI Flash support 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
 2023-10-25 17:05:24 +02:00
Florent Kermarrec 69dc666177 CHANGES: Update. 2023-10-25 16:01:45 +02:00
enjoy-digital cdeb4412f8
Merge pull request #1808 from hansfbaier/master 
Xilinx: Initial openxc7 toolchain support
 2023-10-24 08:41:12 +02:00
Hans Baier f3f46e8cf1 openxc7 toolchain: auto generate chipdb, if missing 2023-10-24 12:01:35 +07:00
Hans Baier 8d0f08a57e fix syntax errors 2023-10-24 08:52:49 +07:00