70eae5cbf9
interconnect/wishbone: increase WB address width to 31
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This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).
FIXME: CI complains about assertions re. axi_lite.address_width in
relationship to len(wishbone.adr) and wishbone_adr_shift, which
seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
but seems to work fine on Rocket.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
foo
2020-08-03 16:11:26 -04:00
b8c9da81ea
soc/interconnect/axi: add Wishbone2AXI converter
2020-08-03 12:50:00 -04:00
2ec4604c41
cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut.
2020-08-03 18:47:17 +02:00
c1ae7e596c
build/sim: allow for arbitrary clocks generation using clockers
2020-08-03 17:06:38 +02:00
38054874ac
build/sim: use a real timebase in the simulation
2020-08-03 15:21:24 +02:00
5e53e5d73a
Merge pull request #615 from pepijndevos/openfpgaloader
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Add openFPGALoader programmer
2020-08-03 14:01:50 +02:00
79ca4d9640
remove debugging
2020-08-01 11:07:04 +02:00
f6e20700d4
add openFPGAloader programmer
2020-08-01 11:05:09 +02:00
eab0726cc8
cpu/vexriscv/core: use variant name as human_name.
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Allow it to be shown in the BIOS and help support.
2020-07-31 08:59:53 +02:00
e0a763e534
cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache.
2020-07-31 08:58:30 +02:00
3ff1bcaf05
cpu/zynq7000: set csr map to 0x00000000.
2020-07-30 21:37:25 +02:00
c0253e3f77
Merge pull request #611 from antmicro/jboc/axi-lite
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soc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 14:22:21 +02:00
cc8440549f
tools/litex_server/read_merger: review/simplify a bit.
2020-07-30 13:58:40 +02:00
4f382ccf55
Merge pull request #605 from cklarhorst/feature-uart-read-merger
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Merge sequential reads for the UART litex_server backend
2020-07-30 13:56:48 +02:00
e78d950a31
soc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 13:50:34 +02:00
a942e358b9
cpu/blackparrot: minor cleanups, add sim variant (since use different flist).
2020-07-30 12:10:32 +02:00
86e910dfaa
Merge pull request #610 from Dolu1990/vexriscv_smp
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soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth
2020-07-29 18:11:00 +02:00
023ab15ec1
soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth
2020-07-29 12:40:16 +02:00
e5cd5d5466
Merge branch 'master' into vexriscv_smp
2020-07-29 11:14:09 +02:00
1938ce363d
integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram.
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This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
2020-07-29 11:10:05 +02:00
6576416b8e
cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing.
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Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to
the DMA bus of Rocket when the direct memory bus is used.
2020-07-29 09:35:15 +02:00
789a70e7c8
Merge branch 'master' into vexriscv_smp
2020-07-28 19:11:54 +02:00
d284dfbea9
soc/cores/cpu/vexriscv_smp config update
2020-07-28 19:07:02 +02:00
0696b409ab
CHANGES: update.
2020-07-28 18:37:23 +02:00
fe38e12b21
cpu/vexriscv_smp: move litedram import, remove os.path import.
2020-07-28 18:10:32 +02:00
59b95fad9c
litex_setup: fix vexriscv-smp repository.
2020-07-28 16:56:32 +02:00
9d052f3830
Merge pull request #607 from Dolu1990/vexriscv_smp
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soc/cores/cpu/vexriscv_smp integration
2020-07-28 16:53:55 +02:00
aa57c7a25e
soc/cores/cpu/vexriscv_smp integration
2020-07-28 16:20:16 +02:00
f87513ab92
liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
2020-07-28 14:36:49 +02:00
9518ccf453
integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone).
2020-07-27 19:57:29 +02:00
9e07623b61
integration/soc: fix dma_bus typo.
2020-07-27 11:06:09 +02:00
2034c563b0
Merge sequential reads for the UART litex_server backend
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The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).
Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
18s (with this merge function)
The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.
2020-07-26 13:19:32 +02:00
1fdffdfd6b
targets: keep in sync with litex-boards.
2020-07-24 16:34:17 +02:00
8a0684b15e
Merge pull request #604 from antmicro/jboc/axi-lite
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Improve AXI Lite data width converters
2020-07-24 14:54:11 +02:00
879e6ffe73
soc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 13:47:18 +02:00
ed7211989f
Merge pull request #603 from enjoy-digital/socdoc-extensions
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Socdoc extensions
2020-07-24 16:42:23 +08:00
29b2baf927
doc: socdoc: document new `sphinx_extra_config` parameter
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This allows for appending additional configuration to `conf.py`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 16:32:01 +08:00
3d16838d67
Merge pull request #602 from enjoy-digital/socdoc-extensions
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doc: socdoc: document `sphinx_extensions` parameter
2020-07-24 10:02:06 +02:00
dd366467ed
litex: add `sphinx_extra_config` to `generate_docs()`
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This allows us to append additional strings to the sphinx `conf.py`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 16:01:54 +08:00
7fecfbf8e0
doc: socdoc: document `sphinx_extensions` parameter
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This adds documentation for `sphinx_extensions` which can be used to add
additional features to output.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-07-24 15:47:59 +08:00
32160e615f
soc/interconnect/axi: separate AXI Lite converter channels
2020-07-24 09:25:57 +02:00
8337039915
CHANGES: update.
2020-07-23 18:02:58 +02:00
041c7527ce
core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.
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This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.
An example is available on litex-boards.
2020-07-23 17:40:46 +02:00
8bdf6941a3
liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency).
2020-07-22 23:15:36 +02:00
8f92034ddd
CHANGES: update.
2020-07-22 23:10:26 +02:00
99e88dfc0b
Merge pull request #600 from antmicro/jboc/axi-lite
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Implement AXI Lite interconnect
2020-07-22 23:03:07 +02:00
d38048baac
soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency).
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When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.
This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
2020-07-22 18:44:37 +02:00
a9d8b81385
test/axi: move all AXI Lite tests to separate file
2020-07-22 17:16:33 +02:00
367eb12240
soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
2020-07-22 17:16:33 +02:00
8ae501c391
test/axi: add crossbar stress tests
2020-07-22 17:16:33 +02:00
Gabriel Somlo
Florent Kermarrec
Jędrzej Boczar
Pepijn de Vos
Dolu1990
Christian Klarhorst
Sean Cross