Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
1246 commits 42 branches 14 tags 31 MiB
Commit graph

1246 commits

This branch
This branch
All branches
Author SHA1 Message Date
William D. Jones
6370acd968 Xilinx Platforms now use cmd.exe on Windows instead of bash to run scripts 
(remove MSYS dependency)
 2015-06-19 00:30:22 +02:00
Florent Kermarrec
f8b1152b98 wishbone: add Cache (from WB2LASMI) 2015-06-17 15:31:49 +02:00
Yann Sionneau
6e876c63ad pipistrello: fix FPGA speed grade 2015-06-14 23:19:27 +02:00
Florent Kermarrec
33b536e505 migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter) 2015-06-02 19:29:38 +02:00
Florent Kermarrec
79624ce849 migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq
fd16b66bdf genlib/cdc: add BusSynchronizer 2015-06-02 17:40:42 +08:00
Sebastien Bourdeauducq
57102ec160 setup.py: valid version number (fixes issue #12) 2015-05-28 15:43:31 +08:00
Florent Kermarrec
a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec
9cabcf14e9 migen/genlib/record: add leave_out parameter to connect 
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
 2015-05-23 13:59:09 +02:00
Guy Hutchison
5390540d3c example of instance usage 2015-05-20 01:14:42 +08:00
Florent Kermarrec
ada131dbe0 vpi: avoid some code duplication between windows and linux 2015-05-13 10:48:08 +02:00
Florent Kermarrec
f6624b34f0 migen/actorlib/spi: apply missing CSR renaming 2015-05-13 10:17:31 +02:00
Florent Kermarrec
76302d7aa6 vpi: cleanup (thanks sb) 2015-05-13 10:13:14 +02:00
Florent Kermarrec
98cf103c65 vpi: fix and simplify windows simulation (ends of msg were ignored) 2015-05-13 03:03:34 +02:00
Florent Kermarrec
b0f159421c Merge branch 'master' of https://github.com/m-labs/migen 2015-05-12 16:16:24 +02:00
Florent Kermarrec
88a406ebec migen/genlib/misc: replace Timeout with WaitTimer from artiq 2015-05-12 16:14:58 +02:00
Yann Sionneau
9194fe43a1 travis: install conda dependencies after activating the virtual env 2015-05-12 14:06:16 +02:00
Yann Sionneau
c1088f4666 travis: get-anaconda.sh does not take args anymore 2015-05-12 13:58:08 +02:00
William D. Jones
fe6eef7069 Windows simulation support 2015-05-09 21:09:52 +08:00
Robert Jordens
99fb0d4619 ise: move -user_new_parser to xst_opt 2015-05-08 11:18:45 +08:00
Florent Kermarrec
70bc4ecb59 mibuild/platforms/pipistrello: add _n suffix to usb fifo pins 2015-05-01 15:49:33 +02:00
Florent Kermarrec
aea7308051 mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap 2015-05-01 15:48:42 +02:00
Sebastien Bourdeauducq
01e2343978 doc: remove cordic 2015-05-01 14:07:38 +08:00
Alain Péteut
96bff77c36 add examples tests 2015-05-01 00:50:17 +08:00
Florent Kermarrec
1cbc468bda migen/actorlib/packet: add Packetizer and Depacketizer 2015-04-28 18:44:05 +02:00
Florent Kermarrec
0da9311d70 migen/genlib: avoid use of floating point in reverse_bytes 2015-04-27 21:04:18 +02:00
Florent Kermarrec
3ce5ff3722 migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer) 2015-04-27 15:14:38 +02:00
Florent Kermarrec
f976b1916a migen/actorlib/misc: add BufferizeEndpoints 
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
 2015-04-27 15:12:01 +02:00
Florent Kermarrec
e96ba1e46f migen/genlib/misc: add reverse_bytes 2015-04-27 15:08:10 +02:00
William D. Jones
472665b81d Add a command line option (-use_new_parser yes) to Xilinx XST to force use of the newer parser for older FPGAs. 2015-04-25 23:01:07 +08:00
Florent Kermarrec
73a1687562 migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?) 2015-04-24 13:24:52 +02:00
Florent Kermarrec
67702f25ab migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
Florent Kermarrec
bc30fc57e7 migen/fhdl: give explicit names to syntax specialization when asic_syntax is used 2015-04-24 12:14:14 +02:00
Florent Kermarrec
61c3efc5f5 migen/test: rename asic_syntax to test_syntax and simplify 2015-04-24 12:00:46 +02:00
Yann Sionneau
b93df693a4 travis: add conda package generation and upload + build doc 2015-04-23 14:15:31 +08:00
Yann Sionneau
7280bdb9d4 Add conda recipe for Migen 2015-04-23 14:15:15 +08:00
Yann Sionneau
2f45d4640b doc: fix warnings during doc build 2015-04-23 12:34:17 +08:00
Guy Hutchison
e5b170f02d travis: install verilator 2015-04-22 12:30:03 +08:00
Guy Hutchison
7ec0ecae11 test: add test for asic_syntax 2015-04-22 12:29:07 +08:00
Alain Péteut
6b5969732a add Travis CI badge 2015-04-22 12:20:46 +08:00
Guy Hutchison
28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
Tim 'mithro' Ansell
b8bbaaef3a Fixing shadowing of global index function. 
Fixes the following warnings;
```
cc -Wall -O2  -fPIC -Wall -Wshadow -g -O2 -fstack-protector --param=ssp-buffer-size=4 -Wformat -Wformat-security -I/usr/include/iverilog -c  -o ipc.o ipc.c
ipc.c: In function ‘ipc_receive’:
ipc.c:98:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
ipc.c:113:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
```

Fixes https://github.com/m-labs/migen/issues/14
 2015-04-21 00:26:07 +08:00
Sebastien Bourdeauducq
f57ee296a9 mibuild/altera: cleanup 2015-04-20 17:17:34 +08:00
Sebastien Bourdeauducq
65eeb33329 Revert "add I/O standard definitions to mibuild/altera" 
This reverts commit a889b41060.
 2015-04-20 16:22:32 +08:00
Alain Péteut
a889b41060 add I/O standard definitions to mibuild/altera 2015-04-20 10:08:47 +02:00
Alain Péteut
1b050d98ea add differential in/out support to mibuild/altera 2015-04-20 10:08:26 +02:00
Alain Péteut
fd966d70ba some PEP8 cosmetic 2015-04-20 10:03:08 +02:00
Florent Kermarrec
15625236c1 platforms/kc705: add PCIe pins 2015-04-17 00:51:16 +02:00
Florent Kermarrec
083d371af4 mibuild: add support for libraries, move .replace("\\", "/") to generic_platform.py and execute it only on Windows machines. 
We need to support libraries when Migen is used as a wrapper on large VHDL designs using libraries.
 2015-04-17 00:11:31 +02:00
Sebastien Bourdeauducq
ae503bc7b9 travis: disable email notification 2015-04-14 23:45:33 +08:00