Commit Graph

54 Commits

Author SHA1 Message Date
Florent Kermarrec 67aaf09b53 link: SATALinkLayer skeleton 2014-11-11 12:29:37 +01:00
Florent Kermarrec 294855e292 phy: use primitives dict and use only sata.std 2014-11-11 10:19:24 +01:00
Florent Kermarrec 30964db4a1 phy: send 2 ALIGN primitives every 256 DWORDs 2014-11-11 09:57:43 +01:00
Florent Kermarrec 353e7fc13b link: add SATALinkLayer skeleton (wip) 2014-11-04 22:55:31 +01:00
Florent Kermarrec 8f6354f2a3 link: improve crc_tb/ preamble_tb and increase length 2014-11-04 17:06:03 +01:00
Florent Kermarrec c810009387 link: add Scrambler and testbench 2014-11-04 16:40:21 +01:00
Florent Kermarrec 8062298668 link: add CRC and testbench 2014-11-04 10:33:11 +01:00
Florent Kermarrec 449daedab7 sata/link: add crc and scrambler C models from SATA specification 2014-11-03 18:11:14 +01:00
Florent Kermarrec 47b5ff5e33 move code and create a directory for each layer 2014-11-03 17:38:12 +01:00
Florent Kermarrec 25e0ccae9a remove DRP ports (won't be used for now) 2014-10-28 11:33:15 +01:00
Florent Kermarrec 3f7406a937 various fixes and simplifications, SATA1 & SATA2 OK 2014-10-28 02:15:19 +01:00
Florent Kermarrec e2cbb3a048 platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows) 2014-10-24 12:32:08 +02:00
Florent Kermarrec bbfce2b707 ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl 2014-10-16 10:38:26 +02:00
Florent Kermarrec b284819d18 revert simulation design and add wave 2014-09-30 11:10:15 +02:00
Florent Kermarrec 110580eb2e add .payload. to Sink and Source to be compatible with upstream Migen 2014-09-30 11:03:36 +02:00
Florent Kermarrec f5001751d0 instanciate GTXE2_COMMON (seems recommended in AR43339) 2014-09-30 10:57:52 +02:00
Florent Kermarrec cf084fd079 test to visualize OOB with Miscope 2014-09-30 10:17:15 +02:00
Florent Kermarrec bc5b23b808 use SGMII clk (125MHz) and SFP for test on KC705 2014-09-30 09:07:15 +02:00
Florent Kermarrec d47917e480 simplify and clean up 2014-09-30 00:50:03 +02:00
Florent Kermarrec 0791b9e2e4 sim working 2014-09-29 17:12:02 +02:00
Florent Kermarrec b47153fbfa fix alignment (still some transmissions errors --> need to check clocks and resets) 2014-09-29 15:37:35 +02:00
Florent Kermarrec ed752758b0 fix and simplify ctrl fsms, OOB OK, align KO 2014-09-27 17:45:46 +02:00
Florent Kermarrec 2f769e4e4e gtx: add resynchronization on control signals 2014-09-27 17:26:05 +02:00
Florent Kermarrec f23c5aa724 mmcm: configure default divider with default_speed 2014-09-27 16:22:40 +02:00
Florent Kermarrec 45f7f8aff5 add tx_reset_fsm and rx_reset_fsm 2014-09-27 16:10:39 +02:00
Florent Kermarrec c27f24c4c0 reorganize code
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
Florent Kermarrec 879478a6e4 clocking: clean up and add comments 2014-09-27 13:33:43 +02:00
Florent Kermarrec 387cf90cf8 host and device communicate with OOB, now need to fix ctrl 2014-09-26 23:30:30 +02:00
Florent Kermarrec 01da43ecb2 reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device. 2014-09-26 22:31:32 +02:00
Florent Kermarrec dfbec91a62 add modelsim simulation and start fixing init 2014-09-26 17:05:05 +02:00
Florent Kermarrec 1d053bd7ee modify TestDesign to be able to simulate phy with host <--> device loopback 2014-09-25 15:37:49 +02:00
Florent Kermarrec 7e14c4fc51 move some logic outside of GTX 2014-09-25 15:23:56 +02:00
Florent Kermarrec c008dfdd98 clean up (thanks to Sebastien) 2014-09-25 14:17:25 +02:00
Florent Kermarrec 435bc22fa0 integrate phy in test design and start fix syntax errors 2014-09-24 16:07:34 +02:00
Florent Kermarrec 18009303ae instanciate device or host controller 2014-09-24 14:00:00 +02:00
Florent Kermarrec 60324295fa manage clock domain crossing and data width conversion in gtx 2014-09-24 13:56:12 +02:00
Florent Kermarrec f436069a04 create sata clock (sata_tx/2 for a 32 bits data path) 2014-09-24 13:55:06 +02:00
Florent Kermarrec 7790105913 realign rxdata / rxcharisk directly in gtx 2014-09-24 12:13:43 +02:00
Florent Kermarrec f74471d027 add device ctrl skeleton (we will use it for simulation with the host) 2014-09-24 11:37:28 +02:00
Florent Kermarrec d78cae1b57 more ctrl skeleton 2014-09-24 11:07:36 +02:00
Florent Kermarrec 71bfd036d0 add ctrl skeleton 2014-09-24 00:01:01 +02:00
Florent Kermarrec fa509b3365 rearrange code and remove datapath for now 2014-09-23 23:03:32 +02:00
Florent Kermarrec 22ea5b08b0 clean up and add K7SATAGTXReconfig skeleton (empty but we don't need it for now) 2014-09-23 22:40:01 +02:00
Florent Kermarrec 674e0b3581 remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug)
(see http://www.xilinx.com/support/answers/45410.html for more information)
2014-09-23 22:17:08 +02:00
Florent Kermarrec e0fd313ce0 add data path from another design (need to be adapted to SATA specification) 2014-09-23 17:36:11 +02:00
Florent Kermarrec d55db1688b add SATAGTX with RX/TX clocking and reset (no DRP for now) 2014-09-23 17:18:03 +02:00
Florent Kermarrec cbbbf8de8b add dict for fbdiv computation on GTXE2_COMMON 2014-09-23 14:11:14 +02:00
Florent Kermarrec 4aff15bb74 create k7satagtx.py and move GTXE2 primitive inside 2014-09-23 14:03:51 +02:00
Florent Kermarrec 7422b94f90 create GTXE2_CHANNEL & GTXE2_COMMON class / add IO signals and parameters 2014-09-23 13:57:02 +02:00
Florent Kermarrec 1a5a2d10e3 fill GTXE2_COMMON constants parameters and signals for SATA / disconnect unused output ports 2014-09-23 12:01:57 +02:00