Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
587f50cf90
|
doc: new 'specials' API
|
2013-02-22 18:12:42 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
Florent Kermarrec
|
e95e8b03b7
|
- reworking WIP
|
2013-02-22 16:40:49 +01:00 |
|
Sebastien Bourdeauducq
|
44ae20d3c4
|
generic_platform: prefix subsignals
|
2013-02-20 18:27:04 +01:00 |
|
Sebastien Bourdeauducq
|
e82ea19cdc
|
doc: tristates
|
2013-02-19 17:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dfec152422
|
Build FPG file
|
2013-02-19 13:27:43 +01:00 |
|
Sebastien Bourdeauducq
|
3f22930b1f
|
tools: add byteswap
|
2013-02-19 13:22:35 +01:00 |
|
Sebastien Bourdeauducq
|
07120e3c3e
|
bios: use puts for long string
|
2013-02-17 16:21:25 +01:00 |
|
Sebastien Bourdeauducq
|
8247f3a154
|
bios: add build date to banner
|
2013-02-17 14:29:11 +01:00 |
|
Sebastien Bourdeauducq
|
b135d87ca2
|
Makefile: correct bitstream filename
|
2013-02-17 00:12:15 +01:00 |
|
Sebastien Bourdeauducq
|
20003f0ada
|
software: go back to GCC
|
2013-02-16 23:41:42 +01:00 |
|
Sebastien Bourdeauducq
|
244cfbc7a2
|
add README, LICENSE and gitignore
|
2013-02-15 19:56:44 +01:00 |
|
Sebastien Bourdeauducq
|
c56c916129
|
load.jtag: remove CFG_OUT/CFG_IN instructions
|
2013-02-15 19:39:54 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
38c3566717
|
generic_platform: add name
|
2013-02-14 20:02:35 +01:00 |
|
Sebastien Bourdeauducq
|
7ad2f7081b
|
m1crg: fix signal names
|
2013-02-13 23:59:35 +01:00 |
|
Sebastien Bourdeauducq
|
ed4d65f2be
|
generic_platform: fix IO signal set when using existing record objects
|
2013-02-13 23:29:33 +01:00 |
|
Sebastien Bourdeauducq
|
feec035cc8
|
generic_platform: get absolute path for added sources
|
2013-02-12 19:16:00 +01:00 |
|
Sebastien Bourdeauducq
|
63d399b6ad
|
fhdl/autofragment: from_attributes
|
2013-02-11 18:34:01 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
709845e618
|
generic_platform: fix request
|
2013-02-11 17:54:01 +01:00 |
|
Sebastien Bourdeauducq
|
ce6701c6e4
|
platforms/m1: norflash_reset -> norflash_rst_n
|
2013-02-11 17:46:27 +01:00 |
|
Sebastien Bourdeauducq
|
4b78d90aad
|
platforms/m1: add serial pins
|
2013-02-11 17:46:03 +01:00 |
|
Sebastien Bourdeauducq
|
7ff61d8930
|
doc: fix signal desc layout
|
2013-02-10 19:39:18 +01:00 |
|
Sebastien Bourdeauducq
|
d78fc48805
|
Merge branch 'master' of github.com:milkymist/migen
|
2013-02-10 19:03:32 +01:00 |
|
Sebastien Bourdeauducq
|
1794b45ed3
|
doc/dataflow: remove ActorNode
|
2013-02-10 19:03:18 +01:00 |
|
Sebastien Bourdeauducq
|
f2665efbfe
|
doc/dataflow: remove ALA
|
2013-02-10 18:57:03 +01:00 |
|
Sebastien Bourdeauducq
|
b988003878
|
doc: multiple clock domains
|
2013-02-10 18:56:45 +01:00 |
|
Sebastien Bourdeauducq
|
6bca9c8b98
|
doc: do not inline examples as this never works with most Sphinx setups ...
|
2013-02-10 18:45:06 +01:00 |
|
Sebastien Bourdeauducq
|
3f063db281
|
doc: update to new Migen APIs
|
2013-02-10 18:42:47 +01:00 |
|
Sebastien Bourdeauducq
|
f68fcef90c
|
tb: use default runner
|
2013-02-09 17:09:29 +01:00 |
|
Sebastien Bourdeauducq
|
92b67df41c
|
sim: default runner to Icarus Verilog
|
2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
bd6856ba7a
|
flow/perftools: finish removing ActorNode
|
2013-02-09 17:03:48 +01:00 |
|
Sebastien Bourdeauducq
|
f13ad035e1
|
Support for command line arguments
|
2013-02-08 22:23:58 +01:00 |
|
Sebastien Bourdeauducq
|
b092237fa6
|
xilinx_ise: support building files without running ISE
|
2013-02-08 20:31:45 +01:00 |
|
Sebastien Bourdeauducq
|
7b8e8a19f3
|
Support adding Verilog/VHDL files
|
2013-02-08 20:25:20 +01:00 |
|
Sebastien Bourdeauducq
|
32dcfc6d02
|
generic_platform: support name remapping
|
2013-02-08 18:27:46 +01:00 |
|
Sebastien Bourdeauducq
|
9ecfdeccec
|
platforms/rhino: add PCA9555 I2C expander
|
2013-02-08 17:44:13 +01:00 |
|
Sebastien Bourdeauducq
|
fef9d0fc78
|
generic_platform: fix typo
|
2013-02-08 17:43:04 +01:00 |
|
Sebastien Bourdeauducq
|
78f8ec1a53
|
platforms: add M1
|
2013-02-08 17:42:35 +01:00 |
|
Sebastien Bourdeauducq
|
25882c6c83
|
platforms: ROACH (incomplete)
|
2013-02-07 22:38:33 +01:00 |
|
Sebastien Bourdeauducq
|
fb5130fc1f
|
Initial version
|
2013-02-07 22:07:30 +01:00 |
|
Florent Kermarrec
|
21b6772448
|
- fix timings.py
|
2013-01-27 13:59:44 +01:00 |
|
Sebastien Bourdeauducq
|
473fd20f8c
|
fhdl/structure: store clock domain name
|
2013-01-24 13:49:49 +01:00 |
|
Sebastien Bourdeauducq
|
3201554f76
|
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
|
2013-01-23 15:13:06 +01:00 |
|
Florent Kermarrec
|
8975fa2e44
|
- update README...
|
2013-01-21 22:40:36 +01:00 |