Sebastien Bourdeauducq
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953e603915
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xilinx_ise: improve parameter passing
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2013-06-01 17:22:57 +02:00 |
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Sebastien Bourdeauducq
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759858f739
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Use migen.fhdl.std
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2013-05-26 18:07:26 +02:00 |
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Sebastien Bourdeauducq
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439f032921
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crg: support for resetless system clock domain
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2013-05-07 19:09:56 +02:00 |
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Sebastien Bourdeauducq
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e4b0e8ed6d
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xilinx_ise: enable register balancing
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2013-05-06 14:21:39 +02:00 |
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Sebastien Bourdeauducq
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85e06cc100
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xilinx_ise: implement NoRetiming synthesis constraint
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2013-04-25 14:57:45 +02:00 |
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Sebastien Bourdeauducq
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29eaf068f3
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xilinx_ise: do not attempt to source settings file on Windows
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2013-04-16 22:55:24 +02:00 |
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Sebastien Bourdeauducq
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31b1960188
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xilinx_ise: add --no-source option to disable sourcing of ISE settings file
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2013-04-16 22:39:35 +02:00 |
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Sebastien Bourdeauducq
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715d332c3d
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crg: apply constraint to IO pins, not internal signals
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2013-04-08 20:28:11 +02:00 |
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Sebastien Bourdeauducq
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8cf7c96a53
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crg: use new platform.request
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2013-03-26 23:08:35 +01:00 |
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Sebastien Bourdeauducq
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3b19dfc412
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Support for platform info
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2013-03-26 19:17:35 +01:00 |
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Sebastien Bourdeauducq
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003f1950cd
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xilinx_ise: fix clock domain names
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2013-03-23 19:37:16 +01:00 |
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Sebastien Bourdeauducq
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4bf3190244
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MultiReg: remove idomain
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2013-03-15 19:54:25 +01:00 |
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Sebastien Bourdeauducq
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6feb6e60b0
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New clock_domain API
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2013-03-15 18:46:11 +01:00 |
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Sebastien Bourdeauducq
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71c8172836
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xilinx_ise/CRG_SE: reset inversion support
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2013-03-15 11:31:36 +01:00 |
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Sebastien Bourdeauducq
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6a412f796e
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xilinx_ise: add lock cycle to bitgen
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2013-03-01 11:29:40 +01:00 |
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Sebastien Bourdeauducq
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2b902fdcbd
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xilinx_ise: import Instance
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2013-02-24 15:36:56 +01:00 |
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Sebastien Bourdeauducq
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d60ab1d215
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Use new 'specials' API
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2013-02-24 12:21:01 +01:00 |
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Sebastien Bourdeauducq
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56ae0f0714
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xilinx_ise: disable SRL extraction on synchronizers
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2013-02-23 19:43:12 +01:00 |
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Sebastien Bourdeauducq
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f13ad035e1
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Support for command line arguments
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2013-02-08 22:23:58 +01:00 |
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Sebastien Bourdeauducq
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b092237fa6
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xilinx_ise: support building files without running ISE
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2013-02-08 20:31:45 +01:00 |
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Sebastien Bourdeauducq
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7b8e8a19f3
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Support adding Verilog/VHDL files
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2013-02-08 20:25:20 +01:00 |
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Sebastien Bourdeauducq
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fb5130fc1f
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Initial version
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2013-02-07 22:07:30 +01:00 |