9762546c95
genlib/cordic: cleanup, documentation, unittests
2013-12-02 12:56:24 +01:00
e54fa6f5f4
migen/test: if SimCase is a TestCase, it's run in every module that imports it
2013-12-02 12:43:14 +01:00
4eef3b9399
migen/test/support: allow easy re-setUp of the testbench with different parameters
2013-12-02 12:42:59 +01:00
138181fa87
make: support build options
2013-12-01 18:19:51 +01:00
de830dc743
mibuild: use keyword arguments directly in build_cmdline
2013-12-01 17:56:07 +01:00
80be6acfd1
mibuild: add support for Yosys
2013-12-01 17:07:48 +01:00
14b50dbb0c
videomixer: config system + store video resolution in flash
2013-11-30 23:07:19 +01:00
cfb9074755
norflash16: fix LSB
2013-11-30 23:06:51 +01:00
352919d17e
norflash: add support for writes
2013-11-30 20:37:56 +01:00
9b0f43e631
doc/index.rst: drop index and table chapter, index and search are also generated without
2013-11-29 23:47:48 +01:00
cbab9d2bff
setup.py: update repository address
2013-11-29 23:26:52 +01:00
5b26fb10a9
genlib/coding: add docstrings, add it to api doc
2013-11-29 23:25:31 +01:00
5ccd1799f2
genlib/coding, test/test_coding: unittests
2013-11-29 23:25:03 +01:00
205908791a
test/test_fifo: do not use relative import
...
This way the test can simply be run with:
python -m unittest test_fifo.py
2013-11-29 23:18:03 +01:00
502a2871bc
test/test_fifo, genlib/fifo: move test to unittest
2013-11-29 23:11:53 +01:00
cb5e0953aa
migen/test: start unittests
2013-11-29 23:11:23 +01:00
55afab2276
sim: use Simulator as a contextmanager
...
__del__ garbage collector callbacks are too delicate. E.g. imported
modules can be garbage collected before the objects using them. Can't
use os.remove, socket.SHUT_RDWR...
* added a DeprecationWarning if a Simulator is garbage collected without
having its .close() called
* renamed all gc __del__ callbacks to close()
* implemented context manager hooks for Simulator. Use like
with Simulator(TestBench()) as s:
s.run()
2013-11-29 23:05:15 +01:00
cf0fb5350f
doc/api, index: add fhdl.structure, add index/search
...
genindex is needed to generate links between members and search is
useful for the html docs.
2013-11-29 22:40:37 +01:00
be9fea182d
fhdl/structure: clarify usage restrictions of LHS Cat
2013-11-29 22:35:53 +01:00
a836cbb44e
doc/conf.py: no modindex, no numpydoc warnings
...
* do not generate boring modindex for html and latex outputs
* numpydoc_show_class_members=False, to skip undocumented methods
https://github.com/phn/pytpm/issues/3#issuecomment-12133978
2013-11-29 22:31:59 +01:00
73db4944f1
fhdl.structure: document the API
2013-11-29 22:31:55 +01:00
e469e5e539
genlib.fifo: fix docstring section syntax
2013-11-29 22:31:51 +01:00
e1b31ec455
genlib/fifo: clarify we behaviour when writable=0
2013-11-28 22:31:10 +01:00
6e9e0a60eb
setup API documentation, start by documenting fifos
2013-11-28 22:14:20 +01:00
89eb5ee315
add autodoc, numpydoc and doctest to sphinx to generate API doc
2013-11-28 22:14:16 +01:00
6140fd2594
platforms/papilio_pro: add 2x SPI pins
2013-11-25 15:14:58 +01:00
356178e680
targets/simple: map SPI flash
2013-11-25 15:08:53 +01:00
5953f901c8
spiflash: add read-only variable data width spi flash
...
Signed-off-by: Robert Jordens <jordens@gmail.com>
2013-11-25 14:23:55 +01:00
b49e6f07b2
targets/simple: add GPIO LED
2013-11-25 12:16:20 +01:00
fa741f54fd
specials/Instance: add PreformattedParam
2013-11-25 12:09:51 +01:00
96600ad9d7
set LM32 reset address
2013-11-25 12:09:16 +01:00
7459a849ee
IntegratedBIOS: read only
2013-11-25 10:25:05 +01:00
78cd7a288e
move integrated BIOS code to gensoc
2013-11-25 10:22:14 +01:00
0dfaf6876a
targets: add simple SoC
2013-11-24 23:52:05 +01:00
07d4cc70db
support for bitstream loading on Papilio Pro
2013-11-24 23:51:51 +01:00
08b09fb02a
do not attempt to build SDRAM PHY header when SDRAM is not present
2013-11-24 23:51:29 +01:00
b212e0279d
gensoc: add Papilio Pro ID
2013-11-24 23:50:33 +01:00
4ba796417d
software: do not attempt to build network/sdram drivers when cores are not present
2013-11-24 23:50:09 +01:00
d4063409e1
software/bios: infer flash start from linker
2013-11-24 23:45:03 +01:00
29f7b94e37
bus/wishbone/sram: expose memory component
2013-11-24 23:43:14 +01:00
c5342c5b5c
bus/wishbone: style
2013-11-24 23:42:54 +01:00
6e48682a5e
platforms/papilio_pro: fix clock signal handling
2013-11-24 23:42:31 +01:00
07fc110fc1
allow BIOS data to be passed to design
2013-11-24 22:14:46 +01:00
257185cc9c
rename create_sdram_modules and add register_rom
2013-11-24 20:16:19 +01:00
fca0b968e7
generate linker memory map, move all generated files into the same folder
2013-11-24 19:50:17 +01:00
b95563e45e
add support for external platforms and targets
2013-11-24 16:55:33 +01:00
c514fdc4a3
platforms/m1: use definition compatible with Mixxeo for VGA out
2013-11-24 14:00:22 +01:00
bc2b4a888b
memtest: flush caches, display total error count, use ifdef instead of comment
2013-11-24 13:59:45 +01:00
b1d1f9ecde
make.py: support extra SoC options
2013-11-24 13:59:15 +01:00
fdff1ae5f8
make build system more generic
2013-11-24 13:37:32 +01:00
Robert Jordens
Sebastien Bourdeauducq