6bc9265c2b
setup: add vexriscv_debug to list of entrypoints
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Add the vexriscv_debug program to the list of scripts created when
installing this module. This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:22:11 +08:00
45a649be9b
tools: vexriscv_debug: add debug bridge
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Add a bridge that uses litex_server to go from openocd to wishbone.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:08:06 +08:00
c821a0feab
cores/cpu/vexriscv: create variants: None and "debug", some cleanup
2018-07-05 17:31:23 +02:00
59fa71593d
core/cpu/vexriscv/core: improve indentation
2018-07-05 16:51:40 +02:00
6068f6ce9c
Merge pull request #77 from xobs/debug-vexriscv-enjoy
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Enable support for vexriscv debugging
2018-07-05 16:46:24 +02:00
11e8491547
platforms/arty_s7: keep up to date with Migen
2018-07-05 12:02:14 +02:00
32d5a751db
soc_core: uart: add a reset line to the UART
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Enable resetting the UART by adding a ResetInserter to the UART.
The UART must be reset when resetting the softcore.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
1ef127e06d
soc: integration: use the new cpu_debugging flag for vexriscv
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Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
e7c762c8c3
soc: vexriscv: add cpu debug support
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Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter. With this enabled, a simple Wishbone interface is provided.
The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.
The debug register at address 4 is used to inject opcodes into the
core, and read back the result.
A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:28 +08:00
2024542a3c
vexriscv: verilog: pull debug-enabled verilog
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The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.
Sync the litex repo with the upstream version to take advantage of debug
support.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:27 +08:00
d35dc5cdea
platforms/arty: merge with Migen
2018-07-05 11:18:49 +02:00
fa0215660b
platforms/kc705: keep up to date with Migen
2018-07-05 10:43:26 +02:00
b9f3b49c63
platforms/de0nano: keep up to date with Migen
2018-07-05 10:42:45 +02:00
1628c36aba
README/boards: add precision on Migen's platforms
2018-07-05 10:09:22 +02:00
df99cc66e8
bios/sdram: also check for last read of scan to choose optimal window
2018-07-02 14:12:27 +02:00
8ce7fcb237
bios/main: add cpu frequency to banner
2018-07-02 13:47:18 +02:00
477d224921
bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal.
2018-07-02 13:46:48 +02:00
9e737d3c57
soc/cores/code_8b10b: update (from misoc)
2018-06-29 14:24:44 +02:00
d58eb4ecb7
bios/sdram: use new phy, improve scan, allow disabling high skew
2018-06-28 18:43:48 +02:00
692cb14245
software/bios: fix picorv32 boot_helper
2018-06-28 11:42:43 +02:00
b5ee110e63
bios/sdram: add write/read leveling scans
2018-06-27 15:31:54 +02:00
34b2bd0c28
boards: add genesys2 (platform with clk/serial/dram/ethernet + target)
2018-06-27 11:27:05 +02:00
8edc659d7d
soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)
2018-06-19 11:15:29 +02:00
2c13b701f5
soc/integration/cpu_interface: add shadow_base parameter
2018-06-18 18:01:47 +02:00
78639fa952
Merge pull request #75 from xobs/bios-windows-build
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soc: bios: fix windows build
2018-06-18 11:21:06 +02:00
7444992999
soc: bios: fix windows build
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The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-18 17:13:54 +08:00
18f86881d9
targets: change a7/k7ddrphy imports to s7ddrphy
2018-06-12 15:40:45 +02:00
3e723d152a
soc/cores/cpu: add add_sources static method
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When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
2018-06-12 10:54:20 +02:00
c534250c43
Merge pull request #72 from bunnie/fix_riscv_boothelper
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fix the vexriscv boot helper
2018-05-30 19:35:04 +02:00
7353197e21
fix the vexriscv boot helper
2018-05-31 01:24:22 +08:00
5ab4282e57
Merge pull request #71 from DeanoC/master
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Fix for missing connectors for arty boards
2018-05-29 00:13:59 +02:00
34a9303448
Fix for missing connectors for arty boards
2018-05-24 21:55:52 +03:00
e7d1683e34
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
2018-05-24 08:10:05 +02:00
06162b61cb
README: add list of supported CPUs/Cores and add link to tutorials
2018-05-09 16:28:28 +02:00
6854c7f5fc
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/ )
2018-05-09 15:39:25 +02:00
66229c8c05
add VexRiscv support (imported/adapted from misoc)
2018-05-09 15:03:37 +02:00
f60da4a5dc
add VexRiscv submodule
2018-05-09 14:39:31 +02:00
d149f386c9
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
2018-05-09 13:26:55 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
121eaba722
soc/intergration/soc_core: don't delete uart/timer0 interrupts
2018-05-01 00:46:26 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
43f8c230a7
soc_core: uncomment uart interrupt deletion
2018-04-12 17:23:46 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
4324c6f666
bios/sdram: update kuddrphy initialization procedure
2018-03-08 13:54:30 +01:00
90dcd45f0b
soc/software/main: go to new line at startup
2018-03-07 21:39:10 +01:00
6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
c02b127ef9
Merge pull request #68 from mithro/improve-csr-missing-error-message
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Improving error message when csr name is not found.
2018-03-05 08:38:25 +01:00
Sean Cross
Florent Kermarrec
bunnie
Deano Calver
Dolu1990