fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
c99cc9343f
examples/pytholite: use new APIs
2013-03-12 16:59:24 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
d92ca43cd0
vpi: make it work by default on Arch
2013-03-12 16:51:58 +01:00
907bfa87f4
examples/basic: use new APIs
2013-03-12 16:45:28 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
c06a821452
generic_platform: implicit get_fragment
2013-03-12 16:14:13 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
c4d9734e53
README: update
2013-03-11 20:29:47 +01:00
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
b042757187
Fix Register name conflict between Pytholite and Bank
2013-03-10 19:47:21 +01:00
f93695f60e
bank/eventmanager: use module and autoreg
2013-03-10 19:29:05 +01:00
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
cddbc1157d
bank/description/AutoReg: check that get_memories and get_registers are callable
2013-03-10 18:11:29 +01:00
68fe4c269c
bank/csrgen: BankArray
2013-03-10 00:45:16 +01:00
f1474420df
bank/description: AutoReg
2013-03-10 00:43:16 +01:00
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
4d4d6c1f88
platforms/m1: add video mixer extension board
2013-03-05 23:03:01 +01:00
9b4ca987e0
bus/csr: support memories with larger word width than the bus (read only)
2013-03-03 19:27:13 +01:00
bb5ee8d3bd
fhdl/autofragment: bugfixes + add auto_attr
2013-03-03 17:53:06 +01:00
cc8118d35c
fhdl/autofragment: FModule
2013-03-02 23:30:54 +01:00
d2491828a4
csr/SRAM: prefix page register with memory name
2013-03-01 12:06:12 +01:00
6a412f796e
xilinx_ise: add lock cycle to bitgen
2013-03-01 11:29:40 +01:00
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
d2cbc70190
bank/description: memprefix
2013-02-25 23:14:15 +01:00
a81781f589
fhdl/specials: allow setting memory name
2013-02-25 23:14:03 +01:00
425de02f42
uio/ioo: fix specials
2013-02-25 23:13:38 +01:00
2b902fdcbd
xilinx_ise: import Instance
2013-02-24 15:36:56 +01:00
55ab01f928
fhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-24 13:08:01 +01:00
d60ab1d215
Use new 'specials' API
2013-02-24 12:21:01 +01:00
56ae0f0714
xilinx_ise: disable SRL extraction on synchronizers
2013-02-23 19:43:12 +01:00
ef833422c7
generic_platform/get_verilog: pass additional args to verilog.convert
2013-02-23 19:42:29 +01:00
0321513726
corelogic -> genlib
2013-02-23 19:37:27 +01:00
c2d54f481f
examples/psync: cleanup
2013-02-23 19:14:31 +01:00
6abac5907b
examples/basic/psync: demonstrate the new features
2013-02-23 19:04:11 +01:00
Sebastien Bourdeauducq
Lars-Peter Clausen