6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
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LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
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Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
fdfede2281
Merge pull request #459 from mithro/travis-fix
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Two small Travis-CI related patches
2020-04-09 09:01:59 +02:00
cb7e309966
travis: Run Windows build but allow it to fail.
2020-04-08 23:14:55 -07:00
43242012ea
travis: Use litex_setup.py from the checked out code.
2020-04-08 23:14:55 -07:00
30f5faf9bc
Merge pull request #458 from david-sawatzke/add_triple
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Add riscv64-none-elf triple
2020-04-08 21:39:29 -07:00
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
3575d03faa
.travis.yml: disable windows test (failing for now).
2020-04-07 12:43:29 +02:00
2ca853fd74
README.md: update RISCV toolchain installation.
2020-04-07 12:39:52 +02:00
d770bfbf2e
.travis.yml: remove Python3.5 test.
2020-04-07 12:33:56 +02:00
bc26af0d47
Merge pull request #451 from mithro/multi-os
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Add multiple Python versions, Windows and Mac to Travis CI testing
2020-04-07 12:29:04 +02:00
30d25ffe5b
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
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- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:48:16 +02:00
3f1159fa0b
litex_setup: reorganize a bit, add separators/comments.
2020-04-07 11:05:36 +02:00
926f961bf3
.travis.yml: revert full url for litex_setup.py.
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We want to have an almost identical .travis.yml between LiteX and the Cores.
Using $TRAVIS_BUILD_DIR works for LiteX but will not work for the cores.
2020-04-07 10:55:58 +02:00
447e8d948c
Merge pull request #452 from mithro/riscv-download
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Add GCC downloading via litex_setup.py
2020-04-07 10:51:27 +02:00
3305a65b77
Enable testing on multiple Python versions.
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Makes sure LiteX tests pass on all supported Python versions.
2020-04-06 17:58:12 -07:00
6bd5eae43f
Enable CI for Windows and Mac.
2020-04-06 17:58:12 -07:00
9e324d9e16
Remove symlinking step.
2020-04-06 17:57:32 -07:00
7f0ecddfb2
Use shutil.unpack_archive.
2020-04-06 17:45:55 -07:00
a1dd8fc883
Ignore SSL errors on CI.
2020-04-06 17:36:09 -07:00
2b2aff1274
Improve the path messages a little.
2020-04-06 17:27:24 -07:00
141644d157
Make travis use litex_setup.py for GCC download.
2020-04-06 17:16:55 -07:00
6adabae730
Adding SiFive RISC-V toolchain downloading to litex_setup.py
2020-04-06 16:51:14 -07:00
59b7db63b1
Fix alignments.
2020-04-06 16:51:14 -07:00
e408fb8f08
Merge pull request #450 from mithro/litex-setup-fix
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litex_setup: Use subprocess so failures are noticed.
2020-04-06 23:04:47 +02:00
d781bf2088
Run `litex_setup.py` outside the git clone directory.
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Otherwise it tries to overwrite the litex directory by cloning LiteX
into it.
2020-04-06 11:38:23 -07:00
dd59dac571
litex_setup: Use subprocess so failures are noticed.
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os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.
2020-04-06 11:27:40 -07:00
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
a67ab41835
interconnect/csr: add reset_less parameter.
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In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
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Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
a35df4f7d1
stream: set reset_less to True on datapath signals.
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Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
cf1c5d99b3
Merge pull request #448 from kessam/patch-1
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Fix timing constraints
2020-04-06 11:12:12 +02:00
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
27f00851d0
Merge pull request #447 from antmicro/spi-xip
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Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
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This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
Florent Kermarrec
Tim 'mithro' Ansell
David Sawatzke
kessam
Piotr Binkowski