Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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859c9d8849
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Use new bus API
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2012-02-15 16:55:13 +01:00 |
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Sebastien Bourdeauducq
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506ffab11a
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uart: RX support
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2012-02-07 14:12:23 +01:00 |
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Sebastien Bourdeauducq
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58f4f78d2c
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sram: fix sub-word write
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2012-02-06 23:13:35 +01:00 |
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Sebastien Bourdeauducq
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5dc875de69
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UART: use new bank API and event manager
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2012-02-06 17:45:31 +01:00 |
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Sebastien Bourdeauducq
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b5cb1083ab
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sram: fix WE signal
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2012-02-03 10:38:17 +01:00 |
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Sebastien Bourdeauducq
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8a2646a549
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Remove explicit bus names
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2012-01-27 22:21:08 +01:00 |
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Sebastien Bourdeauducq
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28f00c3a9a
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Add on-chip SRAM
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2012-01-27 22:09:03 +01:00 |
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Sebastien Bourdeauducq
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6fde54c5aa
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Use meaningful class names
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2012-01-21 12:25:22 +01:00 |
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Sebastien Bourdeauducq
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f8d5c27ef8
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Wishbone: omit fixed LSBs
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2012-01-13 17:28:58 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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3b640c45bb
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Use new syntax
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2011-12-18 22:02:05 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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bb21f7584a
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32-device, 8-bit CSR bus
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2011-12-17 15:54:42 +01:00 |
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Sebastien Bourdeauducq
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85fbe07b94
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clkfx module
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2011-12-17 15:00:11 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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738b45dcbd
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Support the new FHDL syntax
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2011-12-16 21:30:22 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |