728afdd758
build/efinix/common: DifferentialInput support
2023-10-02 17:32:49 +02:00
73a28d2c04
build/efinix/ifacewriter: fix LVDS_TX, complete LVDS_RX
2023-10-02 17:32:08 +02:00
97c84ebf27
build/efinix/common: adding DifferentialOutput support
2023-10-02 14:56:23 +02:00
cd1bd73a87
build/efinix/ifacewriter: adding method to generate lvds python code
2023-10-02 14:53:27 +02:00
9842c95ef5
build/efinix/platform: adding method to get resource name based on signal
2023-10-02 14:45:10 +02:00
e8689eb1dc
Merge pull request #1786 from motec-research/json2renode
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litex_json2renode: fix --bios-binary and add --opensbi-binary
2023-09-30 12:41:58 +10:00
f5b7c0d88e
CHANGES: Update.
2023-09-26 13:49:19 +02:00
eda2221a78
Merge pull request #1789 from protech-engineering/protech
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Add Debug support for NEORV32
2023-09-26 13:45:35 +02:00
a0f4c3715d
Update NEORV32 to verion 1.8.9
2023-09-26 11:13:18 +02:00
564f96c6c7
litex_json2renode: fix --bios-binary and add --opensbi-binary
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--bios-binary is reverted to loading the bios into _rom_ as per the documentation and litex defaults
--opensbi-binary is added to load the openSBI binary into the opensbi memory region
The examples documented in the wiki now work again
2023-09-25 19:34:09 +10:00
3d956af81d
core/vexriscv_smp add --hardware-breakpoints INT to allow hardware breakpoint on PC
2023-09-20 09:10:20 +02:00
7d73873741
Merge pull request #1782 from enjoy-digital/ci-dev-test
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Switch CI to litex_setup.py --dev.
2023-09-18 10:02:36 +02:00
e0be028753
litex_setup: Don't do repo init in dev_mode (SSH clone) if running on CI.
2023-09-18 09:20:48 +02:00
04a33c5ddb
CHANGES: Update.
2023-09-18 09:09:45 +02:00
4639c7b39c
Merge pull request #1776 from Dolu1990/nax-smp
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core/naxriscv provide a deployable NaxRiscv SMP
2023-09-18 09:05:43 +02:00
8bd548d453
CHANGES.md: Start listing changes since 2023.08.
2023-09-18 09:02:05 +02:00
46d9d8c780
README: Update sponsors.
2023-09-18 09:02:00 +02:00
b931499c12
build: Remove osfpga skeleton (would need feedbacks & updates).
2023-09-18 09:01:48 +02:00
351a583f1c
Merge pull request #1780 from timkpaine/tkp/version
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update version number to 2023.08
2023-09-18 08:37:57 +02:00
6162a6dc90
update version number to 2023.08
2023-09-17 17:42:53 -04:00
de608ee114
ci: Switch install to --dev.
2023-09-17 21:59:55 +02:00
eb54ec7402
Add Debug support for NEORV32
2023-09-16 10:41:18 +00:00
639462ce46
Merge pull request #1778 from zeldin/issue_1777
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gen/fhdl/verilog: Fix #1777 .
2023-09-15 13:21:38 +02:00
6da1482336
gen/fhdl/verilog: Fix #1777 .
2023-09-14 17:53:51 +02:00
ff3318b20d
Update litex_setup.py with naxriscv smp
2023-09-14 11:25:02 +02:00
a2c2c211c5
Changes.md: Release 2023.08.
2023-09-14 10:47:37 +02:00
51592df260
debug
2023-09-14 07:19:05 +02:00
e2c3a50e99
core/naxriscv allow memory less gen
2023-09-13 23:10:10 +02:00
e8ed93c571
core/naxriscv git fix attempt
2023-09-13 20:41:27 +02:00
2e4ebc8ec3
core/naxriscv git fix attempt
2023-09-13 19:42:16 +02:00
b160507042
core/naxriscv add rvls git
2023-09-13 18:52:40 +02:00
50b9f44d26
make naxriscv dma optional again
2023-09-13 16:23:39 +02:00
d40d76fe4e
fix indent
2023-09-13 16:18:44 +02:00
5e0b8969ee
Provide a deployable naxriscv SMP
2023-09-13 16:16:27 +02:00
c16add73b4
core/vexriscv_smp add --expose-time, which add "clint_time" as output of the cpu.
2023-09-12 10:42:44 +02:00
5d9dd1059d
core/usb_ohci fix generation
2023-09-12 10:41:47 +02:00
d165418719
CHANGES.md: Update.
2023-09-12 09:35:53 +02:00
bcc7e56dc6
build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code.
2023-09-12 09:30:45 +02:00
412f0f59b9
build/io: Add ClkInput/Ouptut to be able to abstract Clk Input/Output primitives.
2023-09-12 09:29:45 +02:00
36ce71d59b
clock/efinix: Avoid manual n parameter and handle it internally.
2023-09-11 10:11:58 +02:00
112f78bde3
cores/vexriscv_smp add risc-v official debug support via --with-privileged-debug
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Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
2023-09-08 16:42:09 +02:00
022bdf3cdc
tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers.
2023-09-08 16:12:04 +02:00
6c30cb8695
litex_setup.py: Use fixed sha1 version of Migen.
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Migen switched from setup.py to pyproject.toml, we'll need to handle this.
2023-09-08 10:41:30 +02:00
fbae6e8e37
CHANGES.md: Update.
2023-09-07 14:27:12 +02:00
e1025c610a
Merge pull request #1769 from Icenowy/gw5a-pll-fix
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clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
2023-09-06 09:15:42 +02:00
e185871267
Merge pull request #1767 from josuah/fix_radiant_platform_detection
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build/lattice/radiant: fix uname() not prefixed by 'os.'
2023-09-06 09:15:01 +02:00
72447a1f49
Merge remote-tracking branch 'origin/master' into nax-smp
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# Conflicts:
# litex/soc/cores/cpu/naxriscv/core.py
# litex/soc/integration/soc.py
2023-09-05 18:14:44 +02:00
943d652362
cores/naxriscv match axi width
2023-09-05 18:13:27 +02:00
99cb46fd3e
build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility
2023-09-05 16:44:47 +02:00
7afe06a60c
clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
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When targeting GW5A-25 ES, the Gowin IDE has a more strict frequency
range.
Change the range when GW5A- is matched to this.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-09-05 16:50:49 +08:00
Gwenhael Goavec-Merou
AndrewD
Florent Kermarrec
Matteo Marzaro
Andrew Dennison
Dolu1990
Tim Paine
Giulio Girardi
Marcus Comstedt
Icenowy Zheng