Sebastien Bourdeauducq
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26ff6f2a9c
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s6ddrphy: style and other minor fixes
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2013-07-10 20:39:53 +02:00 |
Florent Kermarrec
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60f1585fef
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use Migen s6ddrphy, generate sdram init_sequence in cif.py
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2013-07-10 19:56:09 +02:00 |
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Sebastien Bourdeauducq
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611c4192b1
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Use migen.fhdl.std
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2013-05-22 17:10:13 +02:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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48aae9bee5
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Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
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2013-03-18 17:44:01 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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0caac2246d
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Use new 'specials' API
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2013-02-24 13:07:25 +01:00 |
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Sebastien Bourdeauducq
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5649e88a90
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Use Mibuild
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2013-02-11 18:23:06 +01:00 |
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Sebastien Bourdeauducq
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8bf6945dfd
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Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
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Sebastien Bourdeauducq
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c86dd3cbef
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Define clock domains instead of passing extra clocks as regular signals
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2012-09-11 00:21:07 +02:00 |
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Sebastien Bourdeauducq
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5931c5eb59
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Basic support for new clock domain and instance API
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2012-09-10 23:47:06 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |