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Author SHA1 Message Date
Sebastien Bourdeauducq
df2306ab88 try to use the new anaconda-client 2015-07-31 13:46:28 +08:00
whitequark
eb643f1132 Export _cache_init from crt0.S. 2015-07-31 02:40:52 +03:00
whitequark
90314052fa Implement a dynamic linker. 2015-07-31 02:38:38 +03:00
whitequark
66839b512a Update libunwind submodule. 2015-07-31 02:38:38 +03:00
Florent Kermarrec
106e4c6962 bios/sdram: fix error_cnt computation in memtest 2015-07-30 23:59:04 +02:00
whitequark
94cb3cbcf6 libbase: define intptr_t. 2015-07-30 10:55:12 +03:00
whitequark
4b6bd43d8e Enable ror, ffl1 and addc for OR1K. 2015-07-30 10:55:01 +03:00
whitequark
8db098dd8f Make sure the BIOS file ends on an aligned boundary. 
If it does not, the address to which mkmscimg.py writes the CRC
and the address from which it is read could differ.
 2015-07-29 12:30:57 +03:00
whitequark
a4e14f1058 Don't build base libraries and BIOS with -fPIC after all. 2015-07-29 12:09:05 +03:00
Sebastien Bourdeauducq
abbb76ce84 ise: do not use LCK_cycle:6 by default 2015-07-29 11:09:42 +08:00
Sebastien Bourdeauducq
b7aff65ca9 mor1kx: enable ADDC, CMOV and FFL1 instructions 2015-07-29 00:08:21 +08:00
Sebastien Bourdeauducq
f2eff4d10e soc: increase default BIOS size 2015-07-28 22:36:42 +08:00
Florent Kermarrec
5e6178598c Merge branch 'master' of https://github.com/m-labs/misoc 2015-07-28 11:59:48 +02:00
Florent Kermarrec
405efc5560 update lm32 with "Switch to -fPIC" changes. 2015-07-28 11:11:11 +02:00
whitequark
03ebc736b2 Pass -integrated-as to clang. 
This avoids misdetection of target assembler by clang.
 2015-07-28 11:51:28 +03:00
Robert Jordens
a11d065546 pipistrello: fix cts/rts 
* use the same perspective as for tx/rx (flipped w.r.t. the ftdi chip)
* add pullups in case target or host attempt to use handshaking
 2015-07-27 21:46:24 -06:00
Sebastien Bourdeauducq
b7784fcbd7 platforms/kc705: add GPIO SMA 2015-07-28 00:19:39 +08:00
Sebastien Bourdeauducq
f32f9be17a resetless -> reset_less 2015-07-27 11:46:11 +08:00
Sebastien Bourdeauducq
cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains 2015-07-27 01:51:52 +08:00
whitequark
50cf70140b Update libbase/linker-sdram.ld with -fPIC support. 2015-07-26 16:15:02 +03:00
whitequark
c8ffd0c9ee Switch to -fPIC. 
Using -fPIC for everything allows to link the MiSoC static libraries
both into static images such as the BIOS as well as
into shared libraries.
 2015-07-26 16:06:48 +03:00
whitequark
a8cd3b9adc Remove useless includes pulled in by libunwind. 
These aren't used by libunwind in any configuration and
should be also removed in upstream.
 2015-07-26 13:12:23 +03:00
whitequark
f6639c1833 Add libunwind. 2015-07-26 12:59:18 +03:00
whitequark
24463a168a Add a stub getenv() implementation. 
This is not strictly necessary to build libunwind (it can
be built with -DNDEBUG), but it will be handy while it is
debugged.

It can be removed afterwards.
 2015-07-26 12:55:52 +03:00
whitequark
b2710e437c Add a stub pthread header. 
The header implements only the pthread rwlock interface, which
never actually locks.

This is necessary to build libunwind.
 2015-07-26 12:54:40 +03:00
whitequark
b5048f6cf1 Add headers for the dynamic linker interface. 
These are required for libunwind to discover
the exception frame headers.
 2015-07-26 12:53:18 +03:00
whitequark
7a9975ab5a Add a stub C++ standard library. 
This is necessary to build libunwind.
 2015-07-26 12:49:21 +03:00
whitequark
5502cec3da Add basic inttypes.h. 
This is taken from glibc. Only PRI* definitions are imported;
functions are not.
 2015-07-26 12:44:13 +03:00
whitequark
eef1aa77ef Mark abort() as __attribute__((noreturn)). 2015-07-26 12:43:22 +03:00
whitequark
10f719a830 Add support for fprintf(stderr, ...). 2015-07-26 12:42:53 +03:00
whitequark
f5cc6fb72d Don't use clang for anything except or1k. 2015-07-26 10:00:58 +03:00
whitequark
d03dabb460 common.mak: Pass -fexceptions to clang and clang++. 
This results in generation of .eh_frame sections. These sections
can be discarded during final linking, or included if exception
handling is desired. For exception handling to work, all sources
must be built with -fexceptions.
 2015-07-26 03:30:21 +03:00
whitequark
69c2a705bf common.mak: use clang/clang++ to compile C/C++ sources. 
Note that -integrated-as is not active by default on OR1K,
so we're still shelling out to binutils to assemble.
It is not yet possible to build everything using -integrated-as.
 2015-07-26 03:28:37 +03:00
whitequark
0f47876d2e common.mak: remove RANLIB. 
`ranlib` is not necessary on any system we can possibly build for,
as it is superseded by `ar s` for the last ten years or so (at least).
Thus, change ar invocations to `ar crs`, also removing a `l` flag
that is ignored by binutils.
 2015-07-26 03:20:23 +03:00
whitequark
f500b906e6 common.mak: remove AS. 
$(AS) was never used: $(assemble) invokes the C compiler instead.
In case of LLVM, this will allow us to consistently use the LLVM
internal assembler for both inline assembly in C and assembly
sources; so, avoid ever invoking binutils as explicitly.
 2015-07-26 02:46:03 +03:00
Florent Kermarrec
8d1c555e36 misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq. 
An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
 2015-07-25 00:25:09 +02:00
Florent Kermarrec
ce11b30140 misoclib: integrate mxcrg.py in mlabs_video target, remove others directory 
we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)
 2015-07-24 23:16:45 +02:00
Florent Kermarrec
b75b93df43 misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case. 2015-07-24 14:05:54 +02:00
Florent Kermarrec
0a115f609e litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads) 2015-07-24 13:52:57 +02:00
Sebastien Bourdeauducq
5a535ef347 Revert "migen/actorlib/fifo: add FIFO wrapper function" 
This reverts commit d0a19c4be8.
 2015-07-24 19:25:36 +08:00
Florent Kermarrec
d0a19c4be8 migen/actorlib/fifo: add FIFO wrapper function 
Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
 2015-07-24 13:02:54 +02:00
Florent Kermarrec
d73d75007e misoclib/com/uart: cleanup and add irq condition parameters 
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
 2015-07-24 12:57:42 +02:00
Florent Kermarrec
1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old 
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
 2015-07-24 12:48:51 +02:00
Florent Kermarrec
b1ea3340f3 litepcie/frontend/dma: add loop counter (useful to detect missed interrupts) 2015-07-22 22:55:11 +02:00
Florent Kermarrec
493f424ebd Merge branch 'master' of https://github.com/m-labs/migen 2015-07-22 21:46:23 +02:00
Florent Kermarrec
dfc207aacb litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow) 2015-07-22 21:44:53 +02:00
Florent Kermarrec
5713ae381a actorlib/packet/Depacketizer: manage layouts without error signal 2015-07-22 21:43:21 +02:00
Florent Kermarrec
40740d3ddc litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files 
We should eventually try to use python package_data or data_file for that.
 2015-07-22 18:09:04 +02:00
Sebastien Bourdeauducq
84514cf8d5 uart: remove option to refill HW from uart_write 2015-07-19 23:41:38 +02:00
Robert Jordens
a501d7c52d uart: support async phys 2015-07-19 23:37:00 +02:00