Sebastien Bourdeauducq
7c2d0fa641
indentation
2015-06-17 08:32:17 -06:00
Florent Kermarrec
c0bc94ca1c
soc/sdram: add capability to share L2 cache in multi-CPU SoCs
2015-06-17 15:48:45 +02:00
Florent Kermarrec
f8b1152b98
wishbone: add Cache (from WB2LASMI)
2015-06-17 15:31:49 +02:00
Florent Kermarrec
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
Yann Sionneau
6e876c63ad
pipistrello: fix FPGA speed grade
2015-06-14 23:19:27 +02:00
Florent Kermarrec
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
Florent Kermarrec
571ce5791a
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
...
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
Florent Kermarrec
1bb2580779
sdram: use new Migen Converter in Minicon frontend and small cleanup
2015-06-02 19:37:08 +02:00
Florent Kermarrec
f96a856c97
sdram/phy: fix simphy memory usage
2015-06-02 19:33:09 +02:00
Florent Kermarrec
33b536e505
migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter)
2015-06-02 19:29:38 +02:00
Florent Kermarrec
79624ce849
migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)
2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq
fd16b66bdf
genlib/cdc: add BusSynchronizer
2015-06-02 17:40:42 +08:00
Florent Kermarrec
f40140dba5
sdram: refactor minicon and fix issues with DDRx memories
...
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
Sebastien Bourdeauducq
57102ec160
setup.py: valid version number (fixes issue #12 )
2015-05-28 15:43:31 +08:00
Yann Sionneau
a8b9c126cd
spiflash: now using 64k sectors
2015-05-27 18:44:14 +08:00
Yann Sionneau
3f7e161867
spiflash: cleanup unnecessary parenthesis
2015-05-27 18:44:14 +08:00
Sebastien Bourdeauducq
d50bb8c55e
litesata: more doc fixes
2015-05-26 14:13:13 +08:00
Sebastien Bourdeauducq
1e47cfce2b
Merge branch 'master' of https://github.com/m-labs/misoc
...
Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst
2015-05-26 13:57:26 +08:00
Sebastien Bourdeauducq
a9da892b57
litesata: doc fixes
2015-05-26 13:54:31 +08:00
Florent Kermarrec
989d8a7c29
liteata: fix spelling & mistakes in doc
2015-05-26 07:37:09 +02:00
Florent Kermarrec
eb922f6ddc
litesata: rework frontend doc and add striping, mirroring
2015-05-25 14:04:37 +02:00
Florent Kermarrec
0d1a7b9315
litesata: add mirroring
2015-05-25 14:03:14 +02:00
Florent Kermarrec
c3716296ae
litesata/examples_designs: add striping
2015-05-25 14:02:02 +02:00
Florent Kermarrec
0d2db23603
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
2015-05-25 13:55:15 +02:00
Florent Kermarrec
cb053dc011
liteusb/core/packet: fix missing ,
2015-05-25 13:53:02 +02:00
Florent Kermarrec
1bb5a05488
litesata: add striping module for use of multiple HDDs.
2015-05-23 14:12:20 +02:00
Florent Kermarrec
5daba9af68
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
Florent Kermarrec
a5f495aeac
fhdl/verilog: add reserved keywords
2015-05-23 14:01:08 +02:00
Florent Kermarrec
9cabcf14e9
migen/genlib/record: add leave_out parameter to connect
...
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00
Guy Hutchison
5390540d3c
example of instance usage
2015-05-20 01:14:42 +08:00
Florent Kermarrec
ada131dbe0
vpi: avoid some code duplication between windows and linux
2015-05-13 10:48:08 +02:00
Florent Kermarrec
f6624b34f0
migen/actorlib/spi: apply missing CSR renaming
2015-05-13 10:17:31 +02:00
Florent Kermarrec
76302d7aa6
vpi: cleanup (thanks sb)
2015-05-13 10:13:14 +02:00
Florent Kermarrec
98cf103c65
vpi: fix and simplify windows simulation (ends of msg were ignored)
2015-05-13 03:03:34 +02:00
Florent Kermarrec
b0f159421c
Merge branch 'master' of https://github.com/m-labs/migen
2015-05-12 16:16:24 +02:00
Florent Kermarrec
88a406ebec
migen/genlib/misc: replace Timeout with WaitTimer from artiq
2015-05-12 16:14:58 +02:00
Florent Kermarrec
d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
Yann Sionneau
9194fe43a1
travis: install conda dependencies after activating the virtual env
2015-05-12 14:06:16 +02:00
Yann Sionneau
c1088f4666
travis: get-anaconda.sh does not take args anymore
2015-05-12 13:58:08 +02:00
Florent Kermarrec
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
Florent Kermarrec
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
William D. Jones
fe6eef7069
Windows simulation support
2015-05-09 21:09:52 +08:00
Florent Kermarrec
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
Robert Jordens
99fb0d4619
ise: move -user_new_parser to xst_opt
2015-05-08 11:18:45 +08:00
Florent Kermarrec
4d902b578c
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
2015-05-07 20:03:12 +02:00
Florent Kermarrec
d9111f6a04
litesata: fix packets figure in frontend doc
2015-05-07 11:06:05 +02:00
Sebastien Bourdeauducq
566d973049
README: add note about submodules
2015-05-07 16:29:30 +08:00
Florent Kermarrec
5516a49696
litesata: add doc for frontend
2015-05-06 03:57:07 +02:00
Florent Kermarrec
6908ddbaf9
litesata: cleanup README/doc
2015-05-06 02:02:22 +02:00
Florent Kermarrec
7bdcbc94cd
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
...
Works fine @ 3Gbps, still not working @6.0Gbps
2015-05-06 01:33:02 +02:00
