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Author SHA1 Message Date
Sebastien Bourdeauducq
5d5d5edfe2 spiflash: fix miso bitbang with large DQ 2015-05-06 00:05:25 +08:00
Florent Kermarrec
553262bcc1 soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment... 2015-05-04 12:28:49 +02:00
Florent Kermarrec
438a0856c5 misoclib/cpu: merge git.py in identifier 2015-05-02 18:42:33 +02:00
Florent Kermarrec
da711ad5f1 liteusb: add simple example design with wishbone bridge and software to control it 2015-05-02 18:21:18 +02:00
Florent Kermarrec
c98bd9fd79 rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq) 2015-05-02 17:07:58 +02:00
Florent Kermarrec
145398d874 liteeth/core/mac: minor cleanup 2015-05-02 16:48:57 +02:00
Florent Kermarrec
e9ef11620f liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet) 2015-05-02 16:22:45 +02:00
Florent Kermarrec
1761bfba8a litescope/frontend/wishbone: add support for packetized mode 2015-05-02 16:22:43 +02:00
Florent Kermarrec
ff51bde7f0 liteusb/software/wishbone: optimize writes/reads (send a single packet for a command) 2015-05-02 16:22:40 +02:00
Florent Kermarrec
e8c01ff4aa do more test with last changes fix small issues 2015-05-02 16:22:38 +02:00
Florent Kermarrec
63b8797978 liteeth: move mac to core 2015-05-02 16:22:35 +02:00
Florent Kermarrec
a4617014f4 cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) 2015-05-02 16:22:33 +02:00
Florent Kermarrec
3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Zach Smith
1832f27220 targets/pipistrello: add flash sizes 2015-05-02 09:59:24 +08:00
Florent Kermarrec
5e649a6577 litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized) 2015-05-01 20:45:04 +02:00
Florent Kermarrec
c03c41eb77 litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
Florent Kermarrec
a8b8af220a liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future) 2015-05-01 20:44:59 +02:00
Florent Kermarrec
cd3a51ada6 litescope: fix missing source ack on LiteScopeWishboneBridge 2015-05-01 20:44:57 +02:00
Florent Kermarrec
1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data). 
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
 2015-05-01 17:51:18 +02:00
Florent Kermarrec
23126415d3 litescope: use full name in io.py 2015-05-01 17:49:31 +02:00
Florent Kermarrec
23ba1ccb52 targets/minispartan6: add USBSoC (working, should also be usable on pipistrello) 2015-05-01 16:22:45 +02:00
Florent Kermarrec
da0fe2ecfb liteusb: refactor software (use python instead of libftdicom in C) and provide simple example. 
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
 2015-05-01 16:22:26 +02:00
Florent Kermarrec
603b4cdc8c liteusb: continue refactoring (virtual UART and DMA working on minispartan6) 
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
 2015-05-01 16:11:15 +02:00
Florent Kermarrec
8aa3fb3eb7 com/uart: add tx and rx fifos. 
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
 2015-05-01 15:59:26 +02:00
Florent Kermarrec
70bc4ecb59 mibuild/platforms/pipistrello: add _n suffix to usb fifo pins 2015-05-01 15:49:33 +02:00
Florent Kermarrec
aea7308051 mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap 2015-05-01 15:48:42 +02:00
Sebastien Bourdeauducq
01e2343978 doc: remove cordic 2015-05-01 14:07:38 +08:00
Alain Péteut
96bff77c36 add examples tests 2015-05-01 00:50:17 +08:00
Florent Kermarrec
a6f290ac16 liteusb: add ft2232h_sync_tb 2015-04-28 19:05:34 +02:00
Florent Kermarrec
28c50112a4 liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests 2015-04-28 19:01:03 +02:00
Florent Kermarrec
30eed19283 liteusb: continue refactoring and add core_tb (should be almost OK) 2015-04-28 18:58:38 +02:00
Florent Kermarrec
7fc96da51c misoclib/com/uart: remove liteeth dependency (copy/paste error) 2015-04-28 18:53:46 +02:00
Florent Kermarrec
d253adee61 liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend 2015-04-28 18:51:40 +02:00
Florent Kermarrec
1cbc468bda migen/actorlib/packet: add Packetizer and Depacketizer 2015-04-28 18:44:05 +02:00
Florent Kermarrec
0da9311d70 migen/genlib: avoid use of floating point in reverse_bytes 2015-04-27 21:04:18 +02:00
Florent Kermarrec
453279a7c8 litesata: cleanup link 2015-04-27 15:33:01 +02:00
Florent Kermarrec
0c08055014 Merge branch 'master' of https://github.com/m-labs/misoc 2015-04-27 15:28:08 +02:00
Florent Kermarrec
dc8d844579 liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
Florent Kermarrec
3ce5ff3722 migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer) 2015-04-27 15:14:38 +02:00
Florent Kermarrec
f976b1916a migen/actorlib/misc: add BufferizeEndpoints 
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
 2015-04-27 15:12:01 +02:00
Florent Kermarrec
e96ba1e46f migen/genlib/misc: add reverse_bytes 2015-04-27 15:08:10 +02:00
Florent Kermarrec
91c77d464c liteeth: use new Migen modules from actorlib (avoid duplications between cores) 2015-04-27 15:06:37 +02:00
Florent Kermarrec
20dd6d3047 litepcie: use new Migen modules from actorlib (avoid duplications between cores) 2015-04-27 15:05:40 +02:00
Florent Kermarrec
1ef81c4d24 litesata: split hdd model (phy, link, transport, command & hdd) and update simulations 2015-04-27 14:51:03 +02:00
Florent Kermarrec
ded3f22574 litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores) 2015-04-27 14:48:14 +02:00
Florent Kermarrec
fe867ccf33 litesata: remove icarus_workaround.patch (obsolete) 2015-04-27 14:44:54 +02:00
Sebastien Bourdeauducq
1d9771f574 spiflash: use SoC defines, add write_to_flash function 2015-04-27 13:42:32 +08:00
Florent Kermarrec
0b1a2e1022 liteeth: do MII/GMII detection in gateware for gmii_mii phy 2015-04-26 18:08:07 +02:00
Florent Kermarrec
07b7c2a13f liteeth/phy/gmii: add default value for pads_register 2015-04-26 14:54:54 +02:00
Florent Kermarrec
ae71bf2830 liteeth: fix and improve 10/100/1000Mbps speed auto detection 2015-04-26 14:54:53 +02:00