6d6076d8c6
build/yosys_nextpnr_toolchain: GenericToolchain subclass targeted for toolchains based on Yosys+nextPNR+packer tool suite
2022-07-25 22:00:26 +02:00
32c750c12e
build/nextpnr_wrapper: a NextPNR wrapper
2022-07-25 21:58:44 +02:00
b2adabbece
build/yosys_wrapper: a Yosys wrapper
2022-07-25 21:58:18 +02:00
456822a5fa
tools/litex_json2renode: Add video_framebuffer support
2022-07-25 13:38:12 +02:00
c149f3e4dd
tools/litex_json2renode: Add find_memory_region helper
2022-07-25 13:38:12 +02:00
98168492de
tools/litex_json2renode: Save filtered memory regions for peripheral generators
2022-07-25 13:38:12 +02:00
124a2b2d56
tools/litex_json2renode: Don't disable built-in IRQ controller on vexriscv_smp
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The built-in IRQ controller is needed by linux-on-litex-vexriscv
2022-07-25 13:37:25 +02:00
dae22a0d9d
tools/litex_json2renode: Update PLIC interrupt configuration
2022-07-25 13:30:09 +02:00
212db12b1d
tools/litex_json2renode: Skip braces on MappedMemory registration
2022-07-25 13:25:17 +02:00
4f471490a8
tools/litex_json2renode: Output silenced range start address as hex
2022-07-25 13:25:17 +02:00
74467e3b38
test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI).
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We'll switch back to DUT when AXI Converter will be fixed.
2022-07-25 12:34:38 +02:00
c734732ece
Merge pull request #1386 from sergachev/feature/test_axi_width_conversion
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test: add axi 64b to 32b conversion test
2022-07-25 12:29:42 +02:00
f691aecb95
Merge pull request #1387 from sergachev/fix/cva6
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cpu/cva6: add optional peripheral bus conversion +
2022-07-25 12:22:29 +02:00
8de83550a1
Merge pull request #1385 from sergachev/fix/verilator_includes
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sim: enable relative include paths for verilator
2022-07-25 12:11:04 +02:00
29c2aed64a
Merge pull request #1384 from trabucayre/fix_xilinx_yosys_nextpnr_toolchain
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build/xilinx/yosys_nextpnr: _run_make -> run_script
2022-07-25 12:10:41 +02:00
982f94ba8d
test: add axi 64b to 32b conversion test
2022-07-25 00:20:48 +02:00
20affcfc31
cpu/cva6: add optional peripheral bus conversion to bypass axi width conversion problem; fix add_jtag; cleanup
2022-07-24 23:41:49 +02:00
7613c90fcd
sim: enable relative include paths for verilator
2022-07-24 23:02:41 +02:00
f37a505c46
build/xilinx/yosys_nextpnr: _run_make -> run_script
2022-07-23 15:21:50 +02:00
b9a1fec30f
soc/software: Allow enabling LTO through lto/--lto paramter/argument.
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LTO has been removed by default since causing issues with some CPUs/Toolchains.
For configuration that work corretly, it's still interesting to be able to use it,
this commit allow it through lto/--lto parameter/argument.
2022-07-21 13:15:44 +02:00
e3a536ab5f
soc/SoCBusHandler: Add get_address_width method to get address_width depending bus standard.
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This fixes SDCard/SATA build with and AXI/AXI-Lite Bus.
2022-07-21 12:50:45 +02:00
7acb6d468d
Merge pull request #1380 from antmicro/rkol/f4pga-generictoolchain
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build/xilinx: Fix F4PGA building flow
2022-07-20 14:12:58 +02:00
7a4af24706
Merge pull request #1381 from sergachev/feature/sim_compiler_job_limit
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sim/verilator: add an option to limit the number of compiler jobs
2022-07-20 14:12:23 +02:00
bc62b5ad9f
sim/verilator: add an option to limit the number of compiler jobs
2022-07-20 12:20:25 +02:00
57f8b6810d
build/xilinx: Fix F4PGA building flow
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Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
2022-07-20 10:35:45 +02:00
66015a346e
Merge pull request #1379 from sergachev/axi_tests
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Improve AXI Lite tests
2022-07-20 08:02:31 +02:00
bdf5f19885
Merge pull request #1378 from sergachev/fix/openc906
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cpu/openc906: fix bus name
2022-07-20 08:01:27 +02:00
65d5161408
test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width
2022-07-20 02:44:57 +02:00
bffd59726c
test/axi_lite: rename a test for clarity; parametrize address and data width; add another test call with 64b data width
2022-07-20 02:43:43 +02:00
2edf594fe9
cpu/openc906: fix bus name
2022-07-19 23:50:34 +02:00
dccdc236a6
tools/litex_client: Add --host argument to allow specifying Host's ip address.
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Useful when LiteX server is run on a remote machine and script development is done
directly on dev machine.
2022-07-19 16:10:14 +02:00
25c0eed258
cores/gpio: Add optional reset value.
2022-07-19 16:06:49 +02:00
2d386a4e9f
Merge pull request #1376 from gatecat/gatecat/es-postfix-fix
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oxide: Fix ES postfix on device name
2022-07-19 13:54:31 +02:00
0f3dfbfd26
oxide: Fix ES postfix on device name
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-07-19 10:54:49 +01:00
0654279a8f
Merge pull request #1375 from stnolting/neorv32_system
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[cores/neorv32] add CPU cache and interrupt management functions
2022-07-19 11:25:35 +02:00
f705439235
[neorv32] add interrupt management functions
2022-07-18 20:19:02 +02:00
8d14b9d26b
[neorv32] add cache flush functions
2022-07-18 20:18:50 +02:00
764f29fab7
Merge pull request #1374 from enjoy-digital/neorv32_litex_wrapper
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Improve NeoRV32 support.
2022-07-18 15:56:48 +02:00
2faef0eedc
cpu/neorv32/core: Add variants support.
2022-07-18 15:51:35 +02:00
7687b977a3
cpu/neorv32: Remove litex_core_complex (Can now directly use upstream version).
2022-07-18 15:18:15 +02:00
82fa126e0f
soc/cpu Update NaxRiscv
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- Fix internal LSU dead lock
- Add FPU support
- Should be ok to run debian
- Improve soc integration timings
2022-07-15 18:25:31 +02:00
96ba7ae79e
cores/leds: Add polarity support.
2022-07-14 12:24:41 +02:00
dd8645ca40
Merge pull request #1369 from zeldin/ecp5_pll_manual_placement
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cores/clocks/lattice_ecp5: Allow manual placement
2022-07-13 16:51:49 +02:00
e21deaed0a
Merge pull request #1367 from suppamax/cva6_uart_irq
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CVA6 using UART irq instead of polling
2022-07-13 16:51:22 +02:00
1c51feb21d
cores/clocks/lattice_ecp5: Allow manual placement
2022-07-13 11:14:58 +02:00
ad20e7786e
Merge branch 'master' into cva6_uart_irq
2022-07-11 21:32:06 +02:00
e79e3af6e1
remove UART_POLLING for cva6
2022-07-11 21:31:43 +02:00
2b5a942427
Merge pull request #1362 from zeldin/usb_remote_fix
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remote: usb: fix multi-word reads and writes
2022-07-11 09:36:24 +02:00
9e43ff4722
build/efinix: Fix typo.
2022-07-08 10:12:17 +02:00
553236e042
remote: usb: fix multi-word reads and writes
2022-07-07 22:53:14 +02:00
Gwenhael Goavec-Merou
Piotr Wojnarowski
Florent Kermarrec
Ilia Sergachev
Rafal Kolucki
gatecat
stnolting
Dolu1990
Marcus Comstedt
Massimiliano Giacometti