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Author SHA1 Message Date
Matthias Breithaupt 2fd8c2cd61 sim: add HW_PREAMBLE_CRC for ethernet 
This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble
is automatically attached by the tap, there is no need to add it from
the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set.

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-09-12 10:07:43 +02:00
enjoy-digital b41a526e81
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac 
soc.py: add_ethernet: add mac addr constant
 2024-09-11 11:54:14 +02:00
enjoy-digital 11c7b69fd4
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix 
bios: boot.c: fix warnings
 2024-09-11 11:53:52 +02:00
Fin Maaß 7b3f1509d1
soc.py: add_ethernet: add mac addr constant 
add mac addr constant to add_ethernet,
so it matches the one from add_etherbone.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-09-11 11:21:53 +02:00
Fin Maaß 3966e3438c
bios: boot.c: fix warnings 
this fixes the warnings, when compiling.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-09-11 11:15:56 +02:00
Gwenhael Goavec-Merou dc8b74cc58
Merge pull request #2060 from Dolu1990/efinix-rework 
build/efinix: add a few IO primitives, IO constraints, sdc rework
 2024-09-10 18:40:10 +02:00
Gwenhael Goavec-Merou a80f290d80 soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name 2024-09-10 18:07:34 +02:00
Gwenhael Goavec-Merou ad09ffc150 soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str 2024-09-10 18:03:12 +02:00
Gwenhael Goavec-Merou 109ae17e9e build/efinix/common.py: replaced i as str by a ClockDomain 2024-09-10 17:56:49 +02:00
Florent Kermarrec 458e0057f2 soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths. 2024-09-09 18:24:14 +02:00
Florent Kermarrec 5cd1a57080 soc/interconnect/wishbone: Cosmetic cleanup on Cache. 2024-09-09 18:16:40 +02:00
enjoy-digital e06045c576
Merge pull request #2059 from Dolu1990/vexii-clk-video 
soc/cores/vexiiriscv: update clocks + add video framebuffer support
 2024-09-09 14:12:50 +02:00
Dolu1990 2db93c8e78 core/vexiiriscv: improve l2 timings 2024-09-06 16:07:05 +02:00
enjoy-digital a1a3e846ac
Merge pull request #2058 from VOGL-electronic/bios_add_spiram 
bios: add spiram
 2024-09-06 08:32:11 +02:00
Fin Maaß bd03c496a1 bios: add spiram 
add spiram in bios, so it can enable QPI.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-09-05 16:31:32 +02:00
Dolu1990 599c6dde37
litex/build/efinix/common.py add EfinixDDRTristate binding 
Co-authored-by: Fin Maaß <info@finmaass.de>
 2024-09-05 16:12:32 +02:00
Dolu1990 c0fddb6561 build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled 2024-09-05 15:21:12 +02:00
Dolu1990 642cfbe9a7 soc/cores/vexiiriscv: update clocks + add video framebuffer support 2024-09-05 15:16:15 +02:00
Dolu1990 e62d84b77b Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support" 
This reverts commit 0ea6dd91aa, reversing
changes made to fa47c62b6d.
 2024-09-05 15:15:49 +02:00
Dolu1990 0ea6dd91aa soc/cores/vexiiriscv: update clocks + add video framebuffer support 2024-09-05 15:14:46 +02:00
enjoy-digital fa47c62b6d
Merge pull request #2057 from Dolu1990/usb_ohci_phy_fix2 
core/usb_ohci: fix SDRTristate clock
 2024-09-05 14:40:34 +02:00
Dolu1990 f512c65077 vexiiriscv git update 2024-09-05 13:17:22 +02:00
Dolu1990 2190ca403a core/usb_ohci: fix SDRTristate clock 2024-09-05 10:24:45 +02:00
Florent Kermarrec f67b39739e soc/integration/add_ethernet: Expose full_memory_we parameter. 2024-09-05 10:18:12 +02:00
Dolu1990 1f2418de3b core/usb_ohci: fix SDRTristate clock 2024-09-05 10:17:22 +02:00
Dolu1990 84e7e816c7 efinix: pll now force the generated clock into cd.clk *WARNING* 2024-09-05 10:16:43 +02:00
Andrew Dennison d3161ad74c build/efinix/platform: fix get_pin_name() 
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.

Also only adds slice index for slices with more than one io for cleaner
naming.

("i2c", 0,
    Subsignal("scl", Pins(...)),
    Subsignal("sda", Pins(...)),
),
("i2c", 1,
    Subsignal("scl", Pins(...)),
    Subsignal("sda", Pins(...)),
),

Before:
    output wire          i2c0_oe,
    input  wire          i2c0_scl,
    input  wire          i2c0_sda,
    input  wire          i2c1_scl,
    input  wire          i2c1_sda,
    input  wire          i2c_scl0_IN,
    input  wire          i2c_scl0_IN_1,
    input  wire          i2c_scl0_IN_2,
    output wire          i2c_scl0_OE,
    output wire          i2c_scl0_OE_1,
    output wire          i2c_scl0_OE_2,
    input  wire          i2c_sda0_IN,
    input  wire          i2c_sda0_IN_1,
    input  wire          i2c_sda0_IN_2,
    output wire          i2c_sda0_OE,
    output wire          i2c_sda0_OE_1,
    output wire          i2c_sda0_OE_2,

After:
    output wire          i2c0_oe,
    input  wire          i2c0_scl,
    input  wire          i2c0_scl_IN,
    output wire          i2c0_scl_OE,
    output wire          i2c0_scl_OUT,
    input  wire          i2c0_sda,
    input  wire          i2c0_sda_IN,
    output wire          i2c0_sda_OE,
    output wire          i2c0_sda_OUT,
    input  wire          i2c1_scl,
    input  wire          i2c1_scl_IN,
    output wire          i2c1_scl_OE,
    output wire          i2c1_scl_OUT,
    input  wire          i2c1_sda,
    input  wire          i2c1_sda_IN,
    output wire          i2c1_sda_OE,
    output wire          i2c1_sda_OUT,
 2024-09-04 14:42:45 +02:00
enjoy-digital eda553aeaa
Merge pull request #2056 from trabucayre/altera_agilex5_asyncresetsynchronizer 
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
 2024-09-03 17:54:27 +02:00
Gwenhael Goavec-Merou d0215001f4 build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut 2024-09-03 17:47:40 +02:00
Dolu1990 a90ab9dcca efinix: Merge pt.sdc to the litex sdc to get constraints right 2024-09-03 12:05:26 +02:00
Florent Kermarrec dc29b6f4e5 CHANGES.md: Update. 2024-09-03 09:44:28 +02:00
Gwenhael Goavec-Merou 4152d22065 Revert "build/efinix/platform: fix get_pin_name()" 
This reverts commit 0cb101da25.

Temporary fix for liteeth/phy/titaniumrgmii regression
 2024-09-03 10:24:38 +02:00
Dolu1990 3de5832b9c vexiiriscv: Now use pll.locked for debug reset 2024-09-03 07:58:24 +02:00
Dolu1990 19b3f24d9f efinix: ifacewriter support drive strength and slew 2024-09-03 07:57:30 +02:00
Dolu1990 e01ce6f948 efinix: ifacewriter support drive strength and slew 2024-09-03 07:55:25 +02:00
Florent Kermarrec 3bdbe1ebcf CHANGES.md: Update. 2024-09-02 14:20:09 +02:00
enjoy-digital af0dc7f98b
Merge pull request #2055 from trabucayre/gowin_apicula_fix 
Gowin apicula fix
 2024-09-02 14:08:07 +02:00
Gwenhael Goavec-Merou babe233407 build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software) 2024-09-01 09:55:01 +02:00
Gwenhael Goavec-Merou 3da470048a build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model 2024-09-01 09:53:24 +02:00
Dolu1990 2f2b292e06 vexii add with-cpu-clk 2024-08-30 18:16:56 +02:00
enjoy-digital 15cd556750
Merge pull request #2053 from enjoy-digital/hyperram_new 
soc/cores/hyperbus: Full rewrite of HyperRAM core.
 2024-08-30 15:38:59 +02:00
Florent Kermarrec 61b54aa491 soc/integration/soc: Fix add_peripheral. 2024-08-30 12:08:00 +02:00
Florent Kermarrec c554752e8a soc/cores/hyperbus: Add automatic read burst detection. 2024-08-30 11:53:14 +02:00
Dolu1990 c14f1d0816 vexiiriscv add video support 2024-08-30 10:44:36 +02:00
Dolu1990 5fb873d209 efinix: Add support for more IO 2024-08-30 10:44:10 +02:00
Florent Kermarrec 3bde3e9848 soc/cores/hyperbus: Add automatic write burst detection. 2024-08-29 19:20:23 +02:00
Florent Kermarrec fac80c3a51 soc/cores/hyperbus: Full rewrite of HyperRAM core. 
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.

This rewrite provides a base for future development.
 2024-08-29 12:54:09 +02:00
Dolu1990 cc3f13670a Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix 
efinix: Fix PLL with external clock input ifacewriter
 2024-08-28 20:13:03 +02:00
Dolu1990 d4003b8cfa efinix add SCHMITT_TRIGGER support 2024-08-28 19:59:30 +02:00
Gwenhael Goavec-Merou 4ded509444
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix 
efinix: Fix PLL with external clock input ifacewriter
 2024-08-27 09:50:04 +02:00