puts() and putsnonl() are very similar, and can share code.
Reduce code size by making the former call the latter.
Impact for a RISC-V build:
$ size console.o.orig console.o
text data bss dec hex filename
868 0 12 880 370 console.o.orig
832 0 12 844 34c console.o
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
When building with --cpu-type=mor1kx:
litex/soc/software/bios/readline.c: In function 'readline':
litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
271 | case KEY_END:
| ^~~~
litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
297 | case KEY_DEL:
| ^~~~
litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range]
281 | case DEL:
| ^~~~
The C standard does not specify the signedness of "char", hence this
depends on the implementation. On e.g. RISC-V, "char" is unsigned, but
on OpenRISC, it is signed.
Fix this by making the "ichar" variable explicitly unsigned.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
When building the linux-on-litex-vexriscv documentation with Sphinx
v1.8.5:
Sphinx error:
master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found
The default value of "master_doc" was changed from "contents" to "index"
in Sphinx v2[1]. As the LiteX doc system creates "index.rst", it thus
fails to build with Sphinx v1.x.
Explicitly configure "master_doc" to "index", to make it work with all
versions of Sphinx, regardless of the default.
[1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
When using a non-default VexRiscv cluster config, the netlist for that
config needs to be generated. This requires sbt to be installed.
If sbt is missing, an error message is printed:
sh: 1: sbt: not found
This message may easily be lost in the noise, as the build continues, and fails
later with:
ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory
Make the root cause more visible by raising an OSError, and aborting the
build.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
ex reading/writing to scratch register over jtagbone:
In the SoC:
self.add_jtagbone()
Open LiteX Server:
litex_server --jtag
Do the MMAP accesses:
./litex_cli --read 0x4
0x12345678
./litex_clk --write 0x4 0x5aa55aa5
./litex_cli --read 0x4
0x5aa55aa5
Geert Uytterhoeven
Florent Kermarrec
Hans Baier
Jan Kowalewski
Jędrzej Boczar
Konstantin
Guillaume REMBERT
Acathla-fr