Commit Graph

4857 Commits

Author SHA1 Message Date
Florent Kermarrec f9104b201a bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) 2018-07-06 19:22:33 +02:00
Florent Kermarrec c84e189d6a bios/sdram: fix compilation with no write leveling 2018-07-06 16:22:49 +02:00
enjoy-digital b062d4dddc
Merge pull request #79 from xobs/fix-vexriscv-data-read
vexriscv: debug: fix reading DATA register
2018-07-06 13:23:08 +02:00
Sean Cross be8eb5ff84 vexriscv: debug: fix reading DATA register
The REFRESH register accepts an 8-bit address and determines which
register to refresh.  Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.

A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.

Replace this check with an explicit check for 0x00.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 18:22:32 +08:00
enjoy-digital e35be26ebf
Merge pull request #78 from xobs/vexriscv_debug_bridge
Add Vexriscv debug bridge
2018-07-06 11:12:22 +02:00
Sean Cross 6bc9265c2b setup: add vexriscv_debug to list of entrypoints
Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:22:11 +08:00
Sean Cross 45a649be9b tools: vexriscv_debug: add debug bridge
Add a bridge that uses litex_server to go from openocd to wishbone.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:08:06 +08:00
Florent Kermarrec c821a0feab cores/cpu/vexriscv: create variants: None and "debug", some cleanup 2018-07-05 17:31:23 +02:00
Florent Kermarrec 59fa71593d core/cpu/vexriscv/core: improve indentation 2018-07-05 16:51:40 +02:00
enjoy-digital 6068f6ce9c
Merge pull request #77 from xobs/debug-vexriscv-enjoy
Enable support for vexriscv debugging
2018-07-05 16:46:24 +02:00
Florent Kermarrec 11e8491547 platforms/arty_s7: keep up to date with Migen 2018-07-05 12:02:14 +02:00
Sean Cross 32d5a751db soc_core: uart: add a reset line to the UART
Enable resetting the UART by adding a ResetInserter to the UART.

The UART must be reset when resetting the softcore.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
Sean Cross 1ef127e06d soc: integration: use the new cpu_debugging flag for vexriscv
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
Sean Cross e7c762c8c3 soc: vexriscv: add cpu debug support
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter.  With this enabled, a simple Wishbone interface is provided.

The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.

The debug register at address 4 is used to inject opcodes into the
core, and read back the result.

A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:28 +08:00
Sean Cross 2024542a3c vexriscv: verilog: pull debug-enabled verilog
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:27 +08:00
Florent Kermarrec d35dc5cdea platforms/arty: merge with Migen 2018-07-05 11:18:49 +02:00
Florent Kermarrec fa0215660b platforms/kc705: keep up to date with Migen 2018-07-05 10:43:26 +02:00
Florent Kermarrec b9f3b49c63 platforms/de0nano: keep up to date with Migen 2018-07-05 10:42:45 +02:00
Florent Kermarrec 1628c36aba README/boards: add precision on Migen's platforms 2018-07-05 10:09:22 +02:00
Florent Kermarrec df99cc66e8 bios/sdram: also check for last read of scan to choose optimal window 2018-07-02 14:12:27 +02:00
Florent Kermarrec 8ce7fcb237 bios/main: add cpu frequency to banner 2018-07-02 13:47:18 +02:00
Florent Kermarrec 477d224921 bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. 2018-07-02 13:46:48 +02:00
Florent Kermarrec 9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec d58eb4ecb7 bios/sdram: use new phy, improve scan, allow disabling high skew 2018-06-28 18:43:48 +02:00
Florent Kermarrec 692cb14245 software/bios: fix picorv32 boot_helper 2018-06-28 11:42:43 +02:00
Florent Kermarrec b5ee110e63 bios/sdram: add write/read leveling scans 2018-06-27 15:31:54 +02:00
Florent Kermarrec 34b2bd0c28 boards: add genesys2 (platform with clk/serial/dram/ethernet + target) 2018-06-27 11:27:05 +02:00
Florent Kermarrec 8edc659d7d soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) 2018-06-19 11:15:29 +02:00
Florent Kermarrec 2c13b701f5 soc/integration/cpu_interface: add shadow_base parameter 2018-06-18 18:01:47 +02:00
enjoy-digital 78639fa952
Merge pull request #75 from xobs/bios-windows-build
soc: bios: fix windows build
2018-06-18 11:21:06 +02:00
Sean Cross 7444992999 soc: bios: fix windows build
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`.  This command does not exist on Windows, and is unnecessary.

Add a conditional guard to prevent this command from running on Windows.

Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-18 17:13:54 +08:00
Florent Kermarrec 18f86881d9 targets: change a7/k7ddrphy imports to s7ddrphy 2018-06-12 15:40:45 +02:00
Florent Kermarrec 3e723d152a soc/cores/cpu: add add_sources static method
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
2018-06-12 10:54:20 +02:00
enjoy-digital c534250c43
Merge pull request #72 from bunnie/fix_riscv_boothelper
fix the vexriscv boot helper
2018-05-30 19:35:04 +02:00
bunnie 7353197e21 fix the vexriscv boot helper 2018-05-31 01:24:22 +08:00
enjoy-digital 5ab4282e57
Merge pull request #71 from DeanoC/master
Fix for missing connectors for arty boards
2018-05-29 00:13:59 +02:00
Deano Calver 34a9303448 Fix for missing connectors for arty boards 2018-05-24 21:55:52 +03:00
Florent Kermarrec e7d1683e34 litex_term: cleanup getkey and revert default settings on KeyboardInterrupt 2018-05-24 08:10:05 +02:00
Florent Kermarrec 06162b61cb README: add list of supported CPUs/Cores and add link to tutorials 2018-05-09 16:28:28 +02:00
Florent Kermarrec 6854c7f5fc soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) 2018-05-09 15:39:25 +02:00
Dolu1990 66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec c3652935d9 build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
Florent Kermarrec 121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec 39ffa532b0 xilinx/programmer: fix programmer 2018-05-01 00:44:13 +02:00
Florent Kermarrec c001b8eaf6 build/xilinx/vivado: add vivado ip support 2018-04-12 17:55:46 +02:00
Florent Kermarrec 43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec d7c7474670 gen/sim: fix import to use litex simulator instead of migen simulator 2018-04-04 15:40:53 +02:00
Florent Kermarrec b7f7c8d159 build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC" 2018-03-12 09:33:05 +01:00