89bb90fe2a
global: pep8 (E265)
2015-04-13 21:22:46 +02:00
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
728c15213f
global: pep8 (E222)
2015-04-13 20:55:21 +02:00
69764f2e22
global: pep8 (E401)
2015-04-13 20:54:19 +02:00
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
a2c17cdcef
Merge branch 'master' of https://github.com/m-labs/migen
2015-04-13 09:37:03 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
181aeb4791
Add example of hamming generator and checker instances
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--089e01294e809a874205133faa19
Content-Type: text/plain; charset=UTF-8
<div dir="ltr"><br></div>
2015-04-10 16:15:55 +08:00
5d07072783
strace_tailor: make more generic, cleanup
2015-04-10 11:07:16 +08:00
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
8ce683964a
mibuild/tools/write_to_file: use context manager
2015-04-08 19:41:54 +08:00
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
aac953dd90
vivado: support phys_opt
2015-04-04 19:00:22 +08:00
9506f69390
vivado: add support for pre_synthesis_commands
2015-04-04 19:00:01 +08:00
4522956f11
vivado: make _build_files() a method and rename
2015-04-04 18:59:50 +08:00
1d1189506a
mibuild: support multiple specifications of include file and sources
2015-04-04 18:58:02 +08:00
357c807eb1
Merge branch 'master' of github.com:m-labs/migen
2015-04-02 20:23:12 +08:00
ce429841d5
kc705: fix typo in platform file (LPC definition)
2015-04-02 20:21:20 +08:00
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
d67f24ddc7
migen/bank/description: remove support of _r prefix in CSRs
2015-04-02 12:13:22 +02:00
e5ddd1263c
remove redundant xilinx_strace_tailor.sh
2015-03-30 18:58:34 +02:00
b469571afe
move xilinx_strace_tailor to tools
2015-03-30 19:42:11 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
...
This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
...
This reverts commit ea04947519
2015-03-30 19:41:13 +08:00
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
...
This reverts commit 95cfc444e6
2015-03-30 19:41:04 +08:00
15e24b6c10
mibuild/platforms: fix minispartan6
2015-03-30 11:42:14 +02:00
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
21c5fb6f6c
Merge branch 'master' of github.com:m-labs/migen
2015-03-30 00:52:15 +08:00
19a6157478
platforms/lx9_microboard,usrp_b100: fix bitgen opts
2015-03-30 00:44:56 +08:00
263fc47728
platforms/kc705: fix .bin generation with ISE and Vivado
2015-03-29 21:15:20 +08:00
17f3590a7c
platforms/kc705: add iMPACT programmer
2015-03-29 12:15:39 +02:00
72fae61525
Merge branch 'master' of https://github.com/m-labs/migen
2015-03-27 19:22:03 +01:00
20b646bd1a
add tool to build minimal xilinx toolchains
2015-03-27 19:21:47 +01:00
ec080479da
mibuild/sim: use the same architecture we use for others backends
2015-03-27 14:14:49 +01:00
de31103cce
platforms/minispartan6: add ftdi_fifo pins
2015-03-22 11:20:22 +01:00
200979fb81
platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz
2015-03-22 03:37:27 +01:00
7440ccd65b
mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working)
2015-03-21 20:27:11 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Guy Hutchison
Robert Jordens
Yann Sionneau