Sebastien Bourdeauducq
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8d16fde48c
|
fhdl: add simulation functions in fragment
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2012-03-06 13:58:22 +01:00 |
|
Sebastien Bourdeauducq
|
f995e8b92e
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fhdl: check we pass BV to signals
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2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
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fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
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2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
|
1eb348c573
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fhdl: do not attempt slicing non-array signals to keep Verilog happy
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2012-02-06 18:07:02 +01:00 |
|
Sebastien Bourdeauducq
|
629e771fc0
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fhdl/structure: binary constant builder
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2012-02-05 19:32:11 +01:00 |
Lars-Peter Clausen
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2b3f00cbc1
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fhdl/namer: Add support for STORE_DEREF opcode
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2012-02-02 21:15:10 +01:00 |
|
Sebastien Bourdeauducq
|
6a9b59786b
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fhdl/namer: extract variable names with bytecode inspection
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2012-01-28 23:17:44 +01:00 |
|
Sebastien Bourdeauducq
|
5c2df45577
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fhdl: do not prefix instance signal names
|
2012-01-28 11:39:28 +01:00 |
|
Sebastien Bourdeauducq
|
685b5eb08f
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fhdl: support memory read enable
|
2012-01-27 21:39:23 +01:00 |
|
Sebastien Bourdeauducq
|
0cc7e2ac1e
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fhdl: make WRITE_FIRST default
|
2012-01-27 21:35:58 +01:00 |
|
Sebastien Bourdeauducq
|
5405a83ff9
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fhdl: memories working
|
2012-01-27 20:22:17 +01:00 |
|
Sebastien Bourdeauducq
|
a5bd111370
|
fhdl/verilog: clean up signal classification and support memory descriptions
|
2012-01-27 16:54:48 +01:00 |
|
Sebastien Bourdeauducq
|
6b1d775e9f
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fhdl/structure: memory description
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2012-01-27 16:53:34 +01:00 |
|
Sebastien Bourdeauducq
|
d3d5b481fe
|
Include fragment pads in pre-naming dictionary
|
2012-01-20 22:59:40 +01:00 |
|
Sebastien Bourdeauducq
|
039c6d8eb4
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namer/trace_back: behave on None code_context
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2012-01-20 22:52:50 +01:00 |
|
Sebastien Bourdeauducq
|
e9be3241f6
|
Fix instance support
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2012-01-20 22:36:17 +01:00 |
|
Sebastien Bourdeauducq
|
e4f531a739
|
Include unused I/Os in pre-naming dictionary and register signals with name_override
|
2012-01-20 22:20:32 +01:00 |
|
Sebastien Bourdeauducq
|
904d14d4cf
|
Remove NoContext
|
2012-01-20 22:15:44 +01:00 |
|
Sebastien Bourdeauducq
|
05b20d4987
|
Only include context prefix when necessary
|
2012-01-19 19:25:04 +01:00 |
|
Sebastien Bourdeauducq
|
fc473e31eb
|
Fix disjoint namespace test
|
2012-01-19 19:24:43 +01:00 |
|
Sebastien Bourdeauducq
|
00d3eb7989
|
Always include last step in names
|
2012-01-19 18:42:43 +01:00 |
|
Sebastien Bourdeauducq
|
4eac60d181
|
New naming system: second attempt
|
2012-01-19 18:25:25 +01:00 |
|
Sebastien Bourdeauducq
|
bdde97f5fd
|
New naming system beginning to work
|
2012-01-16 18:42:55 +01:00 |
|
Sebastien Bourdeauducq
|
ab8e08a2ed
|
fhdl: new naming system (broken)
|
2012-01-16 18:09:52 +01:00 |
|
Sebastien Bourdeauducq
|
aa8b8da684
|
fhdl: allow None statements
|
2012-01-15 17:45:54 +01:00 |
|
Sebastien Bourdeauducq
|
3c7161cc34
|
flow: saner endpoint management
|
2012-01-15 15:09:44 +01:00 |
|
Sebastien Bourdeauducq
|
b06e70d849
|
corelogic: FSM
|
2012-01-09 16:28:48 +01:00 |
|
Sebastien Bourdeauducq
|
34c69db14a
|
endpoint: add _i/_o suffix on signal names
|
2012-01-07 21:21:46 +01:00 |
|
Sebastien Bourdeauducq
|
cdd9977a40
|
fhdl: better signal naming heuristic
|
2012-01-07 15:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
b6763c28ea
|
constant: equality
|
2012-01-07 12:29:47 +01:00 |
|
Sebastien Bourdeauducq
|
7b395b565e
|
verilog: split comb block, use assign statements
|
2012-01-07 12:19:06 +01:00 |
|
Sebastien Bourdeauducq
|
f209bf6b33
|
convtools -> tools
|
2012-01-07 00:39:28 +01:00 |
|
Sebastien Bourdeauducq
|
3c1dada9cf
|
record: compatibility check
|
2012-01-06 23:00:23 +01:00 |
|
Sebastien Bourdeauducq
|
d7a3bed44c
|
Signal repr
|
2012-01-06 11:20:33 +01:00 |
|
Sebastien Bourdeauducq
|
9366a226bb
|
Convert -> convert
|
2012-01-05 19:27:33 +01:00 |
|
Sebastien Bourdeauducq
|
76db20cd9f
|
fhdl: encapsulate replicated constants
|
2011-12-23 00:35:13 +01:00 |
|
Sebastien Bourdeauducq
|
8a394f9159
|
verilog: comb reset
|
2011-12-22 00:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
4d6be55e9f
|
verilog: break down Convert function
|
2011-12-21 23:08:50 +01:00 |
|
Sebastien Bourdeauducq
|
26e0b817e8
|
verilog: ignore variable property in combinatorial block
|
2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
|
Sebastien Bourdeauducq
|
4f4d809a4e
|
fhdl: better matching of assignment
|
2011-12-18 21:49:48 +01:00 |
|
Sebastien Bourdeauducq
|
dd42b2daff
|
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
|
2011-12-18 21:47:29 +01:00 |
|
Sebastien Bourdeauducq
|
41e2430e2b
|
fhdl: automatic signal name from assignment
|
2011-12-18 21:26:51 +01:00 |
|
Sebastien Bourdeauducq
|
d21e095397
|
fhdl: fix series of if/elif/else
|
2011-12-17 20:31:42 +01:00 |
|
Sebastien Bourdeauducq
|
6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |
|
Sebastien Bourdeauducq
|
ec47394012
|
verilog: support for float parameters in instances
|
2011-12-17 14:59:27 +01:00 |
|
Sebastien Bourdeauducq
|
ee6ca729a2
|
verilog: user-definable reset and clock
|
2011-12-16 22:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |