Sebastien Bourdeauducq
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bf021efa2b
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verilog: fix unary operator conversion
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2011-12-08 21:15:24 +01:00 |
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Sebastien Bourdeauducq
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78f18ad593
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corelogic: round-robin module
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2011-12-08 21:15:02 +01:00 |
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Sebastien Bourdeauducq
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7c99e51b90
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Named buses
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2011-12-08 19:16:08 +01:00 |
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Sebastien Bourdeauducq
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5720a51dad
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wishbone: add missing SEL
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2011-12-08 19:09:32 +01:00 |
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Sebastien Bourdeauducq
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ed05ec5f6a
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instances: signal override
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2011-12-08 18:56:14 +01:00 |
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Sebastien Bourdeauducq
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c43f3da534
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Wishbone declarations
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2011-12-08 18:47:41 +01:00 |
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Sebastien Bourdeauducq
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a6b86168ce
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Simple bus base class
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2011-12-08 18:47:32 +01:00 |
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Sebastien Bourdeauducq
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1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
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fab02f84cb
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fhdl: fix implicit slice index
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2011-12-07 22:21:30 +01:00 |
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Sebastien Bourdeauducq
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82f77180d5
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fhdl: cleanup value bv
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2011-12-07 22:21:10 +01:00 |
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Sebastien Bourdeauducq
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0e8d894a35
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Variable conversion
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2011-12-05 22:00:06 +01:00 |
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Sebastien Bourdeauducq
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4340680704
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Cleanup
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2011-12-05 19:25:32 +01:00 |
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Sebastien Bourdeauducq
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ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
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458cfc8623
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CSR bus definitions
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2011-12-05 00:16:44 +01:00 |
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Sebastien Bourdeauducq
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e099f4d52f
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Reset insertion
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2011-12-04 22:41:50 +01:00 |
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Sebastien Bourdeauducq
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cd8544c758
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Verilog generator
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2011-12-04 22:26:32 +01:00 |
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Sebastien Bourdeauducq
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499b95a519
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Initial import, FHDL basic structure, divider example
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2011-12-04 16:44:38 +01:00 |