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4803 Commits

Author SHA1 Message Date
Tim Ansell 1c1d87f845
Merge pull request #106 from cr1901/data-crt0 
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
 2018-09-22 15:21:35 +01:00
William D. Jones 9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash. 
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
 2018-09-21 10:23:14 -04:00
Florent Kermarrec 01ae7d4235 README: add migen/litex clarification 2018-09-21 07:37:31 +02:00
Florent Kermarrec 15e584d880 targets/sim: generate analyzer.csv 2018-09-20 12:20:48 +02:00
Florent Kermarrec cde72603a1 targets/sim: generate csr.csv 2018-09-20 11:17:18 +02:00
Florent Kermarrec f62df5023f targets/sim: add rom-init 2018-09-20 01:14:00 +02:00
Florent Kermarrec 1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec 9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec 934b08ede8 targets/sim: merge in a single class and ease configuration 2018-09-19 23:59:15 +02:00
Florent Kermarrec bd42b18856 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-09-19 19:21:14 +02:00
Florent Kermarrec 3e77ae788f targets: replace MiniSoC with EthernetSoC 2018-09-19 19:19:50 +02:00
Florent Kermarrec badd992469 targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) 2018-09-19 19:17:32 +02:00
enjoy-digital 537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull 
Icestorm Improvements
 2018-09-18 08:19:09 +02:00
William D. Jones 5c83c88128 Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. 2018-09-17 21:17:24 -04:00
Florent Kermarrec 9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
Florent Kermarrec a44bedd557 bios/sdram: add missing #ifdef 2018-09-13 06:30:37 +02:00
Florent Kermarrec 0e68daebf3 targets: self.pll_sys --> pll_sys 2018-09-13 05:31:35 +02:00
Florent Kermarrec 1468b9f3ba bios/sdram: show all read scans when failing. 2018-09-13 05:26:51 +02:00
Florent Kermarrec 07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec df3f003ecd soc_sdram: update with litedram 2018-09-09 02:13:00 +02:00
enjoy-digital bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram 
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
 2018-09-08 03:55:23 +02:00
William D. Jones bd70ba278b Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. 2018-09-07 21:49:24 -04:00
enjoy-digital 69716852f1
Merge pull request #100 from cr1901/tinyprog-fix 
lattice/programmer: Use --program-image option with tinyprog if addre…
 2018-09-08 03:48:04 +02:00
Florent Kermarrec 12a8944711 soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) 2018-09-07 11:51:17 +02:00
Florent Kermarrec 2b786065b1 targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen 2018-09-07 10:37:15 +02:00
William D. Jones c812321a93 lattice/programmer: Use --program-image option with tinyprog if address is given. 2018-09-07 04:05:49 -04:00
Jean-François Nguyen 26963d62fa libnet/microudp: (WIP) fix endianness issues 2018-09-06 18:43:55 +02:00
enjoy-digital d9d0320d7c
Merge pull request #98 from jfng/fix_typo 
fix typo and unused include
 2018-09-06 18:23:29 +02:00
Jean-François Nguyen 22c0131324 fix typo and unused include 2018-09-06 17:07:14 +02:00
Florent Kermarrec fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Florent Kermarrec 9cfae4dfde setup.py: create litex_sim exec to ease simulation 2018-09-06 08:48:14 +02:00
Jean-François Nguyen 8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec 1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
Tim Ansell c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx 
build/platforms: Add TinyFPGA BX board and programmer.
 2018-09-03 20:49:33 -07:00
William D. Jones 2949262449 build/platforms: Add TinyFPGA BX board and programmer. 2018-09-03 23:39:40 -04:00
Tim Ansell 3cb754da74
Merge pull request #95 from cr1901/lm32-lite 
Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
 2018-09-03 20:13:45 -07:00
William D. Jones ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
Florent Kermarrec 28cd2da24e README: update 2018-08-31 08:44:22 +02:00
enjoy-digital 05c7b9daf4
Merge pull request #94 from cr1901/nextpnr 
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
 2018-08-28 11:46:35 +02:00
William D. Jones 7af89efc70 lattice/icestorm: Add nextpnr pnr as alternate pnr tool. 2018-08-28 05:17:32 -04:00
Tim Ansell 7a14b75cd6
Merge pull request #93 from phlipped/master 
Fix URL for liteUSB
 2018-08-24 14:08:28 +10:00
phlipped 8b51c44506
Fix URL for liteUSB 2018-08-24 14:03:16 +10:00
Tim Ansell 0074bb888c
Merge pull request #91 from cr1901/ignore-fix 
.gitignore: litex/build contains valid source, so exclude from .gitig…
 2018-08-23 13:17:40 +10:00
Tim Ansell ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones dd480eb72c .gitignore: litex/build contains valid source, so exclude from .gitignore. 2018-08-22 23:04:20 -04:00
William D. Jones 3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec 759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec 09776b77e6 sim: run as root only when needed (ethernet module present) 2018-08-22 15:20:28 +02:00
Florent Kermarrec 06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00