ee26f8c5ae
soc_sdram: cosmetic
2018-08-22 13:40:22 +02:00
2db5424ae6
soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
2018-08-22 13:28:23 +02:00
45e9a42c7e
soc_core: add cpu_endianness
2018-08-21 19:10:22 +02:00
3877d0f111
builder: get_sdram_phy_header renamed to get_sdram_phy_c_header
2018-08-21 18:15:57 +02:00
c64e44ef3f
soc_sdram: use new LiteDRAMWishbone2Native and port.data_width
2018-08-21 14:52:28 +02:00
2eeccc5054
vexriscv: update
2018-08-21 11:04:15 +02:00
eecc6f68ed
soc/integration: move sdram_init to litedram
2018-08-20 15:36:51 +02:00
077f939169
Vexriscv: update csr-defs.h
2018-08-18 14:15:43 +02:00
4225c3b87c
update Vexriscv
2018-08-18 14:14:00 +02:00
9547938527
bios/sdram: changes to ease manual read window selection
2018-08-18 13:45:22 +02:00
a760322fbd
litex_server: allow multiple clients to connect to the same server
2018-08-17 16:09:08 +02:00
8a69a47e7b
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
2018-08-17 08:32:32 +02:00
cb5b4ac468
bios/boot: flush all caches before running from ram
2018-08-16 19:47:43 +02:00
650ac18685
sim/verilator: catch ctrl-c on exit and revert default termios settings
2018-08-16 15:13:27 +02:00
0831ad5492
cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf
2018-08-16 10:04:09 +02:00
1610a7f3fb
bios/sdram: fix read_level_scan result
2018-08-14 18:33:36 +02:00
e07ca05749
Merge pull request #86 from pgielda/patch-1
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Fix generating csr.csv file
2018-08-12 19:34:52 +02:00
3c7890cdd4
Fix generating csr.csv file
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Fix generating csr.csv file when no absolute path is given.
2018-08-12 13:37:39 +02:00
9fa234da50
soc/intergration/cpu_interface: typo
2018-08-08 08:53:54 +02:00
22f645adc1
bios/main: use edata instead of erodata
2018-08-07 09:02:09 +02:00
580efecc8c
picorv32: add reset signal
2018-08-07 08:59:34 +02:00
0429ee9f8f
soc/software/bios: add reboot command
2018-08-06 12:23:50 +02:00
da75159814
soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
2018-08-06 12:23:16 +02:00
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
c0989f65dd
soc/cores/cpu: add reset signal
2018-08-06 12:19:23 +02:00
380f8b96dd
Merge pull request #81 from xobs/vexriscv-to-wishbone
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Push Vexriscv debug directly on the Wishbone bus
2018-07-27 11:59:28 +02:00
fb145daced
tools: remove vexriscv_debug
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This program is no longer needed.
The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.
This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:25:33 +08:00
f17b8324d4
vexriscv: reset wishbone bus on CPU reset
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If the CPU is resetting during a Wishbone transfer, assert the ERR line.
Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
c87ca4f1c3
vexriscv: put debug bus directly on wishbone bus
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By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core. Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.
Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
20d6fcac61
add litex_setup script to clone and install Migen, LiteX and LiteX's cores
2018-07-20 10:11:41 +02:00
8a311bf4a6
build/generic_platform: use list for sources instead of set
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Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
2018-07-20 10:01:33 +02:00
df7e5dbcf6
bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup
2018-07-19 12:52:00 +02:00
1564b440eb
soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8
2018-07-19 12:51:16 +02:00
ae62fe076c
setup.pu: fix exclude
2018-07-19 11:35:50 +02:00
c314193cc9
boards/plarforms/genesys2: replace user_dip_sw with user_sw
2018-07-18 12:48:44 +02:00
10dd55fd88
boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter
2018-07-18 11:51:58 +02:00
b19844d196
setup.py: exclude test, sim, doc directories
2018-07-18 09:37:38 +02:00
85308672d3
software/bios/linker: revert data section since required by RISC-V compiler
2018-07-18 09:30:14 +02:00
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read
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vexriscv_debug: use csr read()/write() accessors
2018-07-17 17:31:48 +02:00
41a9e7d9ae
vexriscv_debug: use csr read()/write() accessors
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CSR access widths can be different from register widths. 8-bit
registers are common.
The runtime-generated `read()` and `write()` functions handle this
mapping correctly. When direct register accesses are handled, this
mapping is lost.
Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-17 18:03:58 +08:00
7ecdcaca4b
soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)
2018-07-16 18:40:36 +02:00
a4caa8964a
targets/nexys_video: remove read leveling constants (now automatic)
2018-07-16 09:44:15 +02:00
d825004173
targets/nexys4ddr: s7ddrphy now supports ddr2, working
2018-07-16 09:43:09 +02:00
4f1274e6a6
bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window)
2018-07-16 09:42:09 +02:00
7dbd85a842
soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)
2018-07-10 22:32:51 +02:00
ef1c778446
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
2018-07-10 13:29:32 +02:00
f9104b201a
bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup)
2018-07-06 19:22:33 +02:00
c84e189d6a
bios/sdram: fix compilation with no write leveling
2018-07-06 16:22:49 +02:00
b062d4dddc
Merge pull request #79 from xobs/fix-vexriscv-data-read
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vexriscv: debug: fix reading DATA register
2018-07-06 13:23:08 +02:00
be8eb5ff84
vexriscv: debug: fix reading DATA register
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The REFRESH register accepts an 8-bit address and determines which
register to refresh. Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.
A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.
Replace this check with an explicit check for 0x00.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 18:22:32 +08:00
Florent Kermarrec
Peter Gielda
Sean Cross