5844376d53
soc_core: adapt memory map for mainline Linux with mor1kx
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Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
2019-09-23 15:34:52 +02:00
201218b2c3
boards/targets: increase integrated ROM size if EthernetSoC is used
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Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
2019-09-23 15:34:34 +02:00
ae38fd4244
soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter
2019-09-23 12:59:43 +02:00
8c979565a8
soc_sdram: change l2_size checks order
2019-09-23 10:15:27 +02:00
a9acab99b3
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)
2019-09-23 09:58:47 +02:00
dde6dd027b
integration/builder: avoid specific _generate_standalone_includes
2019-09-23 09:26:47 +02:00
735ea196dd
This will allow it to be built for microwatt out of tree
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:40:54 +02:00
c28086cde8
soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc...
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:35:50 +02:00
f909e4d706
integration/builder: When the CPU is "None", we used to not generate any code.
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With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:31:21 +02:00
8b7d8217a0
Merge pull request #263 from xobs/spi-flash-csrfield
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spi_flash: document register fields
2019-09-20 08:28:19 +02:00
1a6dddd57c
spi_flash: document register fields
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Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 12:42:43 +08:00
4f659ba422
Merge pull request #262 from jersey99/master
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vivado just needs to be in the path for the programmer as well
2019-09-20 06:25:57 +02:00
9ea11cf5ab
vivado just needs to be in the path for the programmer as well
2019-09-19 20:35:55 -07:00
430fee4dbd
Merge pull request #261 from xobs/event-documentation
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csr_eventmanager: add `name` and `description` args
2019-09-19 11:40:55 +02:00
60d8572c3e
csr_eventmanager: add `name` and `description` args
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Add `name` and `description` as optional arguments to the various
EventSource types. These default to `None`, so this should be a
backwards-compatible change.
Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-19 17:23:03 +08:00
e2c78572a2
cores/timer: add general documentation on Timer implementation and behavior.
2019-09-19 09:27:24 +02:00
e97c1e36fb
soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower
2019-09-19 05:36:57 +02:00
99ed0877ac
csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)
2019-09-18 10:47:54 +02:00
f2e84a5800
soc/cores/timer: fix typo (thanks xobs)
2019-09-18 10:45:38 +02:00
28885064f7
soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident.
2019-09-18 10:14:47 +02:00
f1139c36b4
Merge pull request #259 from xobs/document-timer
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timer: add documentation
2019-09-18 09:36:53 +02:00
cb7d941aaa
timer: add documentation
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Now that CSRs have documentation support, add documentation to the basic
`Timer` module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-18 15:06:20 +08:00
cca0478a5e
soc/cores/spi: use new CSRField (no functional change)
2019-09-16 17:02:55 +02:00
80b2bef387
soc/cores/bitbang: use new CSRField (no functional change)
2019-09-16 16:56:00 +02:00
3dc8d29498
Merge pull request #257 from enjoy-digital/csr_fields
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soc/interconnect/csr: add CSRField/documentation support, do some simplification on CSRStorage
2019-09-16 09:16:20 +02:00
9bda614a3e
csr: update copyrights
2019-09-16 08:49:00 +02:00
29134cc659
csr: more documentation
2019-09-16 08:45:29 +02:00
74e756aa30
csr/CSRStorage: remove storage_full (was only needed by alignment_bits)
2019-09-16 08:38:26 +02:00
5dc440e80d
csr: use IntEnum for CSRAccess
2019-09-16 08:36:25 +02:00
d2646f138e
csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful
2019-09-15 19:47:48 +02:00
8e14694eb5
csr/fields: document, add separators, 100 characters per line
2019-09-15 19:11:25 +02:00
4e84729cf9
csr/fields: add access parameter
2019-09-14 22:16:18 +02:00
23b01f8f02
csr/fields: add pulse mode support
2019-09-14 21:49:34 +02:00
8c080e5fb6
soc/interconnect/csr: add initial field support
2019-09-13 20:01:31 +02:00
c120f6d457
build/openocd: add set_qe parameter to flash
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QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.
2019-09-12 17:07:56 +02:00
6a0a1c9d87
tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)
2019-09-12 10:21:37 +02:00
16b6b357ca
soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found
2019-09-11 18:30:28 +02:00
62f53d5035
soc/integration/builder: call do_exit with vns when build is done.
2019-09-10 12:41:05 +02:00
cb5f1467cf
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-09-09 15:12:24 +02:00
004c96b508
soc/itnegration: update litedram
2019-09-09 15:12:08 +02:00
a7b5c18523
Merge pull request #255 from sergachev/fix-crc32
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fix crc32
2019-09-09 13:38:29 +02:00
2400f0f43d
fix crc32
2019-09-09 13:19:43 +02:00
19f58dd971
interconnect/wishbone: add FlipFlop to allow UpConverter to be used
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Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
2019-09-09 11:47:36 +02:00
bd6ec63be4
build/openocd: add stream method for JTAG UART
2019-09-06 11:57:18 +02:00
b356204f95
soc_core: add JTAG UART support (uart_name="jtag_uart)
2019-09-06 11:56:42 +02:00
d0ebbda4b3
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
2019-09-06 11:55:41 +02:00
2638393b53
soc_zynq: fix indent
2019-09-05 15:59:35 +02:00
9051cf97e4
soc_zynq: fix typo
2019-09-05 15:55:18 +02:00
67a09aef05
soc/interconnect/stream: add Monitor module
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Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
2019-09-05 11:54:14 +02:00
6f150a5626
Merge pull request #254 from mithro/crc-smaller
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Add @xobs' smaller CRC version
2019-09-03 07:23:32 +02:00
Filip Kokosinski
Florent Kermarrec
Benjamin Herrenschmidt
Sean Cross
Vamsi K Vytla
Ilia Sergachev