5cc3db0176
soc: cosmetic: reduce horizontal indentation in IRQ init.
2020-11-30 16:29:16 -05:00
9af56cf247
soc: fix typo in IRQ handler exception
2020-11-30 16:27:31 -05:00
d193092e16
cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle.
2020-11-30 12:18:59 +01:00
18f66a79f2
cores/cpu/zynq7000: improve methods to pass provide/pass configuration to PS7.
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User can now only use set_ps7 and provides the .xci file, preset file or/and additional configuration:
To use a .xci file, in the design do:
self.cpu.set_ps7(xci="ps7.xci")
To use a preset:
self.cpu.set_ps7(preset="preset_name")
To use a config dict:
self.cpu.set_ps7(name="ps7_name", config={"param0": "0", "param1": "1"})
It's also possible to use preset and then pass and additionnal config dict:
self.cpu.set_ps7(preset="preset_name")
self.cpu.add_ps7_config({"param0": "0", "param1": "1"})
or all at once:
self.cpu.set_ps7(preset="preset_name", config={"param0": "0", "param1": "1"})
2020-11-30 11:30:48 +01:00
30e8773819
Merge pull request #711 from trabucayre/ps7_config
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zynq7000: add tcl to create zynq IP based on board preset and custom configuration
2020-11-30 10:28:54 +01:00
c8fcaaea2d
integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").
2020-11-30 10:17:03 +01:00
146068b048
integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled.
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This prevents adding peripherals that requires IRQ support to SoC not supporting
them. Enabling is done automatically when a CPU with interrupt support is added,
but this can also be added manually.
2020-11-30 10:06:45 +01:00
d9f9b4aeb6
Merge pull request #713 from daveshah1/dave/rocket-reset-fix
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rocket: Fix UB due to optimised away DFFs
2020-11-28 08:12:33 -05:00
61895bef37
rocket: Fix UB due to optimised away DFFs
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As both clock and async reset for the debug DFFs were 0, and there was
no initial value on them, they were being validly optimised away by
newer Yosys versions to 1'bx which was propagating into and breaking the
core.
This fixes the problem by tying the async resets to the CPU reset
signal.
Signed-off-by: David Shah <dave@ds0.me>
2020-11-28 11:15:42 +00:00
c491c60b7d
soc/cores/prbs/PRBSRX: add pause signal to pause errors counting.
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Simplify CDC when passing the errors to software by allowing the values to stabilized.
2020-11-28 11:33:57 +01:00
869e50ade8
soc/cores/prbs: minor cosmetic cleanups.
2020-11-28 10:27:22 +01:00
e2dcdcf917
build/lattice/programmer/load_bitstream: convert .bit to .svf with bit_to_svf it bitstream_file provided as .bit.
2020-11-28 08:58:57 +01:00
289234b102
build/lattice: add bit_to_svf script from Project Trellis to allow using OpenOCD with Diamond.
2020-11-28 08:58:04 +01:00
08b6d0388c
zynq7000: add tcl to create zynq IP based on board preset and custom configuration
2020-11-28 08:56:47 +01:00
785bc7e86c
build/lattice/diamond: set timingstrict default value to False (similar to others build backends)
2020-11-28 07:56:30 +01:00
52a1622895
README: update ci badges.
2020-11-26 19:13:56 +01:00
e5a7375b30
cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset.
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It seems EHXPLLL does not loose locked when reseted.
2020-11-26 18:56:24 +01:00
b02753ecfa
tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices.
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litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234
Etherbone scan on 192.168.1.x network:
- 192.168.1.20
- 192.168.1.50
2020-11-26 13:33:20 +01:00
4a748a53b8
soc/interconnect/packet: add initial PacketFIFO.
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For now just ensures that we have a full packet in the FIFO before setting source.valid.
It would be nice in the future to also be able to discard packets in the FIFO.
2020-11-26 11:27:42 +01:00
c3660379db
tools/remote/comm_udp: probe Etherbone server on open().
2020-11-26 09:06:52 +01:00
f390161baa
integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel.
2020-11-26 09:06:06 +01:00
896d1ba988
Merge pull request #709 from daveshah1/oxide-build
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Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX
2020-11-25 19:21:11 +01:00
ad62e15d98
tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie.
2020-11-25 16:25:31 +01:00
595c6738a3
tools/remote/etherbone: speed up encoding/decoding.
2020-11-25 16:08:12 +01:00
3d2574a488
tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts.
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This way, user scripts can be use RemoteClient (communicating with the Server that has
already been opened on the right interface) or directly use CommXY in the scripts.
Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between
the client and server). On fixed configuration using CommXY directly can then be faster
and also avoid manual opening of the server.
2020-11-25 15:05:28 +01:00
2c3687983c
tools/litex_server/client: cleanup.
2020-11-25 11:34:12 +01:00
fa9149720f
tools/remote/comm_udp: keep up to date with new encoding/decoding.
2020-11-25 11:33:44 +01:00
c003293b31
tools/remote/etherbone: simplify/speed up decoding.
2020-11-25 11:33:02 +01:00
c0822bac1a
Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX
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Signed-off-by: David Shah <dave@ds0.me>
2020-11-25 09:44:51 +00:00
01e75addff
tools/remove/etherbone: simplify/speed up encoding.
2020-11-25 10:00:28 +01:00
2a1df9beeb
tools/remote/etherbone: replace merge_bytes with direct call to int.from_bytes.
2020-11-25 09:11:33 +01:00
4d5dca2d74
tools/remote/etherbone: replace split_bytes by direct call to int.to_bytes.
2020-11-25 09:07:58 +01:00
9b696373a2
tools/remove/etherbone: cosmetic cleanup, add assert for maximum burst size (255).
2020-11-25 08:53:11 +01:00
6fe2bcd1f0
Merge pull request #708 from antmicro/false_path_constraints
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symbiflow: restore add_false_path_constraint
2020-11-24 18:37:00 +01:00
fe12821a64
Merge pull request #707 from enjoy-digital/github-actions
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ci: migrate from Travis CI to Github Actions.
2020-11-24 16:01:27 +01:00
6771ed0796
ci: migrate from Travis CI to Github Actions.
2020-11-24 15:55:49 +01:00
6684e7ae7a
symbiflow: restore add_false_path_constraint
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Restore the method to fix SymbiflowToolchain class API
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-11-24 15:34:32 +01:00
f918d0bf02
tools/remove: add 0x to hex debug prints.
2020-11-24 14:06:46 +01:00
cddf19df98
integration/soc/add_etherbone: expose buffer_depth.
2020-11-23 17:50:31 +01:00
a1bfa79092
Merge pull request #705 from betrusted-io/reset-docs
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correct the documentation for the ctrl reset register
2020-11-23 17:46:50 +01:00
119062c068
Merge pull request #706 from betrusted-io/master
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add a hook for activating the GSR inside the STARTUPE2 block for spi_opi
2020-11-24 00:29:14 +08:00
33f073a0a9
add a hook for activating the GSR inside the STARTUPE2 block for spi_opi
2020-11-24 00:27:18 +08:00
4d7fe81a07
correct the documentation for the ctrl reset register
2020-11-24 00:19:05 +08:00
9b3414746c
Merge pull request #704 from antmicro/fix-symbiflow-workarounds
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symbiflow: remove workarounds
2020-11-23 15:56:17 +01:00
0431af729c
symbiflow: remove workarounds for symbiflow
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-11-23 10:33:11 +01:00
8e39060d26
Merge pull request #701 from enjoy-digital/csr_eventmanager_cleanup
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interconnect/csr/EventManager: simpifly/cleanup code that documents C…
2020-11-20 03:24:09 +08:00
32989c17b6
soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME.
2020-11-18 22:04:14 +01:00
1ac34bf5bf
Merge pull request #702 from antmicro/fix-disable-build-timestamp
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litex: soc: do not add the timestamp in the BIOS if it was disabled
2020-11-18 22:01:25 +01:00
9440975a1f
cores/ram: cosmetic cleanup.
2020-11-18 21:52:43 +01:00
3c0d41781f
litex: soc: do not add the timestamp in the BIOS if it was disabled
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-11-18 17:36:50 +01:00
Gabriel Somlo
Florent Kermarrec
David Shah
Gwenhael Goavec-Merou
Robert Winkler
bunnie
Alessandro Comodi