ef2ed8bbbc
tools/litex_json2dts: fix vexriscv-smp cpu reg numbering.
2020-12-21 18:16:44 +01:00
5ec5554713
tools/litex_json2dts: cleanup and reorganize peripherals.
2020-12-21 16:11:45 +01:00
df92e2aea7
tools/litex_json2dts: switch VexRiscv to SMP, update SDCard dts.
2020-12-21 16:11:32 +01:00
0a9c9562dc
Merge pull request #738 from antmicro/quartus-handle-includes
...
Quartus: handle vh and svh files
2020-12-21 10:19:27 +01:00
90b9f4eca3
soc/interconnect/axi: fix AXIInterface.get_ios().
2020-12-21 08:51:04 +01:00
7f6af0a437
Quartus: handle vh and svh files
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-12-20 11:53:08 +01:00
7fccf9fcd0
Merge pull request #736 from Disasm/ecpdap
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Add ECPDAP programmer
2020-12-18 15:39:24 +01:00
b7aec66929
soc/interconnect/axi: simplify AXI Full connect_to_pads and get_ios.
2020-12-18 15:35:04 +01:00
57d9816065
Merge pull request #734 from antmicro/axi4-slave-bridge
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Add get_ios for full AXI and add missing signals in connect_to_pads
2020-12-18 15:25:54 +01:00
9ae5a4f4ea
Merge pull request #735 from Dolu1990/vexriscv_smp
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cores/cpu/vexriscv_smp add AES support
2020-12-18 14:43:04 +01:00
f055b1be69
Merge pull request #732 from Disasm/ecp5-compress
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Add option for ECP5 bistream compression
2020-12-18 14:42:34 +01:00
0fe2477f69
Add ECPDAP programmer
2020-12-18 15:42:18 +03:00
ee47c7b260
cores/cpu/vexriscv_smp add AES support
2020-12-18 12:10:33 +01:00
f26769eb4d
interconnect/axi: add connect_to_pads to full AXI
2020-12-18 09:06:45 +01:00
18e90234b0
interconnect/axi: add get_ios to full AXI
2020-12-18 08:59:11 +01:00
2bc76f3245
Add option for ECP5 bistream compression
2020-12-18 00:21:05 +03:00
4092180662
tools/lxterm/json: json file provide relative path, add json file directory to image names.
...
Allow sharing same json file between serial boot and Ethernet/SDCard/SATAboot:
boot.json:
{
"Image": "0x40000000",
"rv32.dtb": "0x40ef0000",
"rootfs.cpio": "0x41000000",
"opensbi.bin": "0x40f00000"
}
If boot.json and images are located in images directory, using lxterm --images=images/boot.json
will now work.
2020-12-17 16:08:32 +01:00
f777cddefe
Merge pull request #731 from lindemer/pmp
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Allow selection of VexRiscv_Secure* from lxsim CLI
2020-12-14 19:41:51 +01:00
c23a894014
Allow selection of VexRiscv_Secure* from lxsim CLI
2020-12-14 10:54:02 +01:00
bc2b7995f5
integration/export/get_csr_header: don't generate replace/write fields access functions when CSR is read only.
2020-12-14 10:51:37 +01:00
649edd189a
Merge pull request #729 from betrusted-io/master
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another minor change - reveal STARTUPE2 block's ring oscillator
2020-12-13 02:19:56 +08:00
422cc2baae
another minor change - reveal STARTUPE2 block's ring oscillator
2020-12-13 01:49:43 +08:00
fb3b09db15
integration/soc/add_uart: add crossover+bridge support.
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Useful to have both CPU UART and bridge debug capability.
2020-12-10 18:32:21 +01:00
88bd754dd6
software: add minimal baremetal demo app.
...
Used to demonstrates how to easily create baremetal apps, boot to it with LiteX and
also ease litex_term testing.
To build it: export BUILD_DIR=xxyy/litex/litex/boards/targets/build/arty && make
To load it: lxterm /dev/ttyUSB1 --kernel=demo.bin
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading demo.bin to 0x40000000 (9264 bytes)...
[LXTERM] Upload complete (9.8KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x40000000
--============= Liftoff! ===============--
LiteX minimal demo app built Dec 10 2020 17:13:02
Available commands:
help - Show this command
reboot - Reboot CPU
led - Led demo
donut - Spinning Donut demo
litex-demo-app> led
Led demo...
Counter mode...
Shift mode...
Dance mode...
litex-demo-app> donut
Donut demo...
$$$$$@@@@@
$##########$$$$$$$$
###*!!!!!!!!!***##$$$$$$
***!!====;;;;===!!**###$$$$#
**!===;;;:::::;:===!!**####$##
!*!!==;;:~-,,.,-~::;;=!!**#######!
!!!!=;:~-,.......-~::==!!***#####*
!!!!==;~~-.........,-:;==!!***###**!
!**!!=;:~-... ..-:;=!!!********!
;!*#####*!!;. ~:;==!!!******!!=
:!*###$$$$#*! :;==!!!!!****!!!=;
~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=;
;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~
-;!*###$$$$$$$###******!!!!!!!===;~
-;!!*####$#####******!!!!!!==;;:-
,:=!!!!**#**#***!!!!!!!====;:~,
-:==!!!*!!*!!!!!!!===;;;:~-
.~:;;========;=;;:::~-,
.--~~::::~:~~--,.
litex-demo-app>
2020-12-10 17:16:28 +01:00
ef6fd57613
Merge pull request #727 from betrusted-io/master
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fix a timing error in the S7 OPI block
2020-12-10 23:17:29 +08:00
ee41fbb338
tools: deprecate litex_jtag_uart (now directly integrated in litex_term).
2020-12-10 15:48:10 +01:00
8ee0fdbf8e
fix a timing error in the S7 OPI block
...
should have no impact on normal operation, the path is
only for registering addresses that are correlated with
ECC errors as reported by the OPI device.
2020-12-10 22:48:09 +08:00
39b84581f4
tools/litex_term: add JTAG UART support (litex_term jtag_uart).
2020-12-10 15:46:12 +01:00
384041affb
tools/litex_term/crossover: use burst to speed up reads.
2020-12-10 14:34:00 +01:00
48dc574703
integration/soc/add_uart: pass fifo_depth to UARTCrossover.
2020-12-10 14:33:29 +01:00
1976fd4b90
tools: deprecate litex_crossover_uart (now directly integrated in litex_term).
2020-12-10 13:54:21 +01:00
feeb2f72e0
tools/litex_term: add direct crossover UART bridge suppport (lxterm --crossover) and switch to multiprocessing.
2020-12-10 13:45:38 +01:00
8a82ddf6e1
CSR fields: generate convenience functions ( #725 )
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Generate convenience methods to extract/replace bits in CSR fields, only generate replace if CSR register is writable.
2020-12-10 11:32:21 +01:00
cd80c87f1a
software/liblitedram/write_leveling: revert ideal_delay to 0, ensure write delay is set just before 0 to 1 transition.
2020-12-09 19:51:19 +01:00
5ebea9434b
software/liblitedram/sdram: improve comments.
2020-12-09 17:53:33 +01:00
44d21cb0f3
Merge pull request #722 from geertu/master
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tools/litex_json2dts: Miscellaneous fixes and improvements
2020-12-08 14:01:14 +01:00
a80398d2ab
Merge pull request #724 from sergachev/master
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soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too
2020-12-08 13:45:12 +01:00
c6fb9ef939
software/liblitedram: limit clk/cmd scan to 1/2 tCK.
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Restrict the clk/cmd scan to 1/2 tCK since the full scan is not required
and in some cases can compromise the calibration with the wrong best clk/cmd
value selection.
This should also allow using cmd_latency=0 in all cases.
2020-12-08 10:01:18 +01:00
c19c343ecf
software/libbase: add memtest_access before testing bus/addr/data to exit early if bus errors are detected.
2020-12-07 14:05:51 +01:00
fb05fbc5cc
software: always provide flush_l2_cache implementation (even if empty) to avoid #ifdefs CONFIG_L2_SIZE.
2020-12-07 13:45:05 +01:00
3ce74f6e29
software/libbase/memtest: cosmetic cleanups.
2020-12-07 13:23:58 +01:00
9af9ee6b66
soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too
2020-12-06 00:23:30 +01:00
bed072ef19
tools/litex_term: use different payload_length/delay settings for USB-ACM.
2020-12-04 19:59:49 +01:00
d8b844bbda
tools/litex_json2dts: Group tuples in liteeth reg property
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To improve human readability and enable automatic validation, the tuples
in "reg" properties should be grouped using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-12-04 16:38:48 +01:00
a17b535906
tools/litex_json2dts: Fix DTS indentation
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Make indentation of the generated DTS more consistent, by always using 8
spaces (no TABs), and aligning continued lines.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-12-04 16:21:52 +01:00
8265d06728
tools/litex_json2dts: Fix SPI bus #size-cells
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As per Documentation/devicetree/bindings/spi/spi-controller.yaml,
"#size-cells" must be zero for a PCI bus.
This gets rid of the following build warnings:
build/orangecrab/orangecrab.dts:105.29-39: Warning (reg_format): /soc/spi@f0004800/mmc-slot@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
build/orangecrab/orangecrab.dts:91.46-110.19: Warning (spi_bus_bridge): /soc/spi@f0004800: incorrect #size-cells for SPI bus
buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Fixes: fafa844aa7
2020-12-04 16:19:29 +01:00
b7c0922ec1
tools/litex_term: increase outstanding to 128 (4 is slowing down speed with USB-FIFO).
2020-12-04 16:01:35 +01:00
894802d131
tools/litex_term: add sfl_outstanding parameter (set to 4), cleanup code and increase inter-frame delay.
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This fixes upload on OrangeCrab with USB-ACM, but we still need to understand why
sfl_payload_length can't be set to 255 with USB-FIFO.
2020-12-04 15:46:18 +01:00
5e10552f3f
soc/interconnect/packet/Packetizer: fix last_be for 10gbe.
2020-12-03 17:11:04 +01:00
168c5380cf
Merge pull request #718 from trabucayre/zynq_fix_constraints
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don't add pins without pad location in constraints file
2020-12-03 16:21:06 +01:00
Florent Kermarrec
Karol Gugala
Vadim Kaushan
Dolu1990
Piotr Binkowski
Samuel Lindemer
bunnie
Stéphane Gourichon
Ilia Sergachev
Geert Uytterhoeven