Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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7d18736ff2
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Update gitignore
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2012-05-17 01:42:08 +02:00 |
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Sebastien Bourdeauducq
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79124d822b
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Identifier
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2012-05-17 01:41:41 +02:00 |
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Sebastien Bourdeauducq
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141269b384
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Get CSR base addresses from include file
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2012-05-16 10:36:46 +02:00 |
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Sebastien Bourdeauducq
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bb798176fc
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Common include files
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2012-05-16 10:20:04 +02:00 |
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Sebastien Bourdeauducq
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b6aa40d845
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bios: automatically enable hardware memory controller and test memory
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2012-05-15 19:29:26 +02:00 |
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Sebastien Bourdeauducq
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425c8b8e70
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asmicon/multiplexer: fix read tag delay
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2012-05-15 13:13:40 +02:00 |
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Sebastien Bourdeauducq
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7ecfd60368
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bios: more DDR diagnostic functions
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2012-05-14 20:07:57 +02:00 |
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Sebastien Bourdeauducq
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2ccdade88e
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tb/asmicon_wb: better access pattern
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2012-04-30 19:08:31 -05:00 |
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Sebastien Bourdeauducq
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87ee4baaf0
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tb/asmicon_wb: test asmicon with wishbone bridge
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2012-04-26 17:53:05 -05:00 |
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Sebastien Bourdeauducq
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902908bd3b
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tb/asmicon: do not keep files
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2012-04-26 17:21:10 -05:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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d2c4afe66c
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asmicon: various fixes. Now produces convincing refresh/read sequences.
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2012-04-01 23:24:24 +02:00 |
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Sebastien Bourdeauducq
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f5671c566f
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tb/asmicon: global test bench
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2012-04-01 23:23:45 +02:00 |
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Sebastien Bourdeauducq
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185bd66ee4
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tb/asmicon: bankmachine test bench
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2012-03-31 18:11:29 +02:00 |
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Sebastien Bourdeauducq
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b1e5b9ef36
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tb/asmicon/bankmachine: test buffer and NACK
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2012-03-31 10:06:44 +02:00 |
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Sebastien Bourdeauducq
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c129c98e10
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tb/asmicon/bankmachine: selector test bench
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2012-03-31 09:56:22 +02:00 |
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Sebastien Bourdeauducq
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ac7d89a4fe
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asmicon/bankmachine: fixes
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2012-03-31 09:55:52 +02:00 |
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Sebastien Bourdeauducq
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bccc5f5c21
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tb: remove obsolete norflash test bench
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2012-03-30 16:41:12 +02:00 |
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Sebastien Bourdeauducq
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c6a4a8f462
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tb/asmicon: refresher test
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2012-03-30 16:40:51 +02:00 |
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Sebastien Bourdeauducq
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cd82f16806
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asmicon/refresher: fix refresh sequence done signal
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2012-03-30 16:26:50 +02:00 |
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Sebastien Bourdeauducq
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ab799b874f
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tools: new flterm
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2012-03-21 09:11:43 +01:00 |
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Sebastien Bourdeauducq
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c26efa28ca
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asmicon: multiplexer (untested)
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2012-03-18 22:11:01 +01:00 |
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Sebastien Bourdeauducq
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0e00837f42
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asmicon: move slot time to timing settings
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2012-03-18 14:57:31 +01:00 |
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Sebastien Bourdeauducq
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b1eb919ad2
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asmicon: bank machine (untested)
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2012-03-18 00:12:03 +01:00 |
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Sebastien Bourdeauducq
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7c377880fa
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asmicon: refresher (untested)
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2012-03-15 20:29:26 +01:00 |
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Sebastien Bourdeauducq
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e3ef121440
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norflash: use new timeline API
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2012-03-15 20:26:04 +01:00 |
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Sebastien Bourdeauducq
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7b14e0bd05
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asmicon: skeleton
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2012-03-14 18:26:05 +01:00 |
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Sebastien Bourdeauducq
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8d4a42887e
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ddrphy: working on hardware, simulation a bit messed up
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2012-02-24 15:44:51 +01:00 |
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Sebastien Bourdeauducq
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baba267db6
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ddrphy: request wrdata_en/rddata_en at the same time as the command
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2012-02-24 15:14:58 +01:00 |
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Sebastien Bourdeauducq
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17b2588321
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ddrphy: reads OK, write data coming out 1/2 cycle too late
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2012-02-24 15:05:52 +01:00 |
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Sebastien Bourdeauducq
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a363eb4a36
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ddrphy: partly working
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2012-02-24 13:54:10 +01:00 |
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Sebastien Bourdeauducq
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3179a27d14
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dfii: set data mask
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2012-02-23 22:00:51 +01:00 |
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Sebastien Bourdeauducq
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92ac69bae3
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dfii: new design
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2012-02-23 21:21:07 +01:00 |
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Sebastien Bourdeauducq
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b3ca952a39
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s6ddrphy: read path OK in simulation
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2012-02-21 17:38:40 +01:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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ce51653381
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s6ddrphy: generate DQ/DQS/DM OE
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2012-02-20 16:13:56 +01:00 |
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Sebastien Bourdeauducq
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cbc3b7fa83
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s6ddrphy: DQ/DQS/DM SERDES
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2012-02-20 13:45:57 +01:00 |
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Sebastien Bourdeauducq
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4c1e18a9b5
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s6ddrphy: clock, address and command
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2012-02-19 20:49:56 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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1e4e092a55
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bios: fix function prototypes
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2012-02-18 21:06:35 +01:00 |
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Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
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5bc840b9c1
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DFI injector (untested)
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2012-02-17 23:50:10 +01:00 |
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Sebastien Bourdeauducq
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c38de34a21
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bios: DDR initialization skeleton
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2012-02-17 18:47:04 +01:00 |
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Sebastien Bourdeauducq
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e5927e265f
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bios: add flash target using m1nor
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2012-02-17 18:16:29 +01:00 |
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Sebastien Bourdeauducq
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48ddbf0c85
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Add build Makefile and JTAG load script
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2012-02-17 18:09:48 +01:00 |
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Sebastien Bourdeauducq
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c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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cdd58e023b
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s6ddrphy: use single-ended DQS
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2012-02-17 10:53:58 +01:00 |
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Sebastien Bourdeauducq
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cc5e4ae710
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clkfx: remove
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2012-02-16 19:30:00 +01:00 |