5c83c88128
Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.
2018-09-17 21:17:24 -04:00
c812321a93
lattice/programmer: Use --program-image option with tinyprog if address is given.
2018-09-07 04:05:49 -04:00
2949262449
build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 23:39:40 -04:00
7af89efc70
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
2018-08-28 05:17:32 -04:00
09776b77e6
sim: run as root only when needed (ethernet module present)
2018-08-22 15:20:28 +02:00
650ac18685
sim/verilator: catch ctrl-c on exit and revert default termios settings
2018-08-16 15:13:27 +02:00
8a311bf4a6
build/generic_platform: use list for sources instead of set
...
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
2018-07-20 10:01:33 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
...
xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection
...
Top module selection (for Verilator and Diamond)
2018-02-19 12:27:25 +01:00
d448874879
sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)
2018-01-23 10:28:16 +01:00
ef511e7edc
Specify top-level module in Lattice Diemond build script.
...
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
2018-01-23 01:17:04 +00:00
ef6c517dad
Build top module as 'dut' in Verilator and set it as top-level.
...
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
2018-01-23 01:15:28 +00:00
ead88ed66d
Support forcing colorama colors on.
...
This is needed if you want colors but are using pipes and similar.
2018-01-18 14:41:45 +11:00
10000eb607
build/xilinx/vivado: only generate constraints that are not empty
2018-01-08 17:03:19 +01:00
ee6b33e9d3
build: add Inverted property to IOs to ease inverting signals and propagate property to cores
2018-01-06 01:33:02 +01:00
282f22f09e
Add tracelength report generation by default to help with board layout
2017-12-27 22:40:39 +08:00
fe2564e921
build/lattice/icestorm: fix missing toolchain_path
2017-12-27 00:26:07 +01:00
5a2c92ba80
Add TinyFPGA platform based on Migen.
2017-12-27 00:00:05 +01:00
f096030fc8
Import Icestorm backend improvements from Migen.
2017-12-26 23:57:13 +01:00
a3390bb403
build/xilinx/programmer: fix settings in run_vivado (update)
2017-12-19 10:29:29 +01:00
4c82eb549f
build/xilinx: add support for edif/ngc files
2017-12-16 13:20:45 +01:00
e07bd71b16
build/xilinx: Fixing settings finding.
...
* Better error messages.
* Search correct directories;
- XXX/Vivado/<version>
- XXX/<version>/ISE_DS/
2017-10-16 18:25:51 +11:00
2c013948b1
Output better error message for flash_proxy.
2017-10-07 12:14:00 +11:00
c3383f47ba
Port IceStorm backend from Migen.
2017-10-03 22:48:44 -04:00
f25e46c428
Merge pull request #26 from q3k/diamond-linux-support
...
Add Diamond toolchain support for Linux.
2017-07-20 14:41:05 +02:00
503df5e93e
Add Diamond toolchain support for Linux.
...
This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
2017-07-20 13:21:10 +01:00
0b6d38abe9
build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer
2017-07-19 14:54:19 +02:00
bd876d4cd6
merge migen 9a6fdea3 changes
2017-06-28 22:47:13 +02:00
4433e2449a
litex/build/sim: cleanup modules
2017-06-28 18:01:04 +02:00
c3710ec139
build/sim: cleanup serial2console and fix terminal mode
2017-06-28 17:38:09 +02:00
5ece895fd3
litex/build/sim: add README
2017-06-28 16:55:32 +02:00
4a0a431119
litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex)
2017-06-28 16:28:45 +02:00
ab6f4de521
litex/build/sim: small cleanup
2017-06-28 16:25:56 +02:00
1d8298af94
litex/build/sim: add tapcfg submodule for ethernet
2017-06-28 16:18:15 +02:00
8510b12e93
litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept)
2017-06-28 16:14:13 +02:00
5f9ff09c08
vivado: Fix segfault with or1k.
...
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
File "./make.py", line 82, in <module>
```
2017-04-29 16:44:18 +10:00
1cda83f11b
build/xilinx/programmer: add target parameter to load_bitstream to select jtag programmer
2017-02-20 17:37:03 +01:00
60f7e9c14f
build/lattice/diamond: add jedec file generation
2017-02-18 17:33:50 +01:00
384f4f428e
build/xilinx/vivado: set_property library only supported for vhdl
2017-02-17 11:42:55 +01:00
5fde6d6d3d
build/lattice/diamond: remove use of tools.mkdir_noerror
2017-02-16 11:48:22 +01:00
William D. Jones
Florent Kermarrec
Sergiusz Bazanski
Tim 'mithro' Ansell
bunnie
Tim 'mithro' Ansell
Pierre-Olivier Vauboin