Commit Graph

10 Commits

Author SHA1 Message Date
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00
Florent Kermarrec de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
2015-03-21 12:55:39 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Florent Kermarrec 6107b7844a test implementation on all targets and fix issues 2015-02-28 12:04:51 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
Florent Kermarrec 074f576340 targets: add de0nano (100MHz, integrated bios and SDRAM) 2015-02-27 19:47:32 +01:00