The next move was to avoid use of soc_core_argdict and prefer use of soc_argdict directly,
so rename method now to avoid use on soc_core_argdict on targets/designs.
Some builds may default to creating position independent executables
with a .dynamic section containing symbols that must be relocated at
runtime. This section appears after .data section and is included in
the output .bin, causing it to be included in the build time CRC
calculation. The runtime CRC calculation stops after .data, so there
was always a mismatch.
The litex bios has no support for relocating the dynamic symbols, so
disable pie on all platforms. This will improve compatibility with
distro toolchains.
Tested with:
marocchino / or1k-elf-gcc (GCC 12.1.0-2 Debian 1.0.3) 12.1.0
vexriscv / riscv64-linux-gnu-gcc (Debian 12.2.0-3) 12.2.0
microwatt / powerpc64le-linux-gnu-gcc (Debian 12.2.0-3) 12.2.0
Signed-off-by: Joel Stanley <joel@jms.id.au>
Currently we create a 32-bit Wishbone bus, connect LiteDRAM to it and
then connect it to the main SoC bus. This prevents us from getting
optimized performance from a wider main bus.
Make the intermediate bus to have the same width with the main bus.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Currently the code only supports 32/64 bit SoC data width.
Add support for any possible data width that is multiply of 32-bit.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
The default ethmac section address conflicts with main_ram defined for
openC906.
Add a custom position of ethmac to the memory map, which directly
follows the internal APB.
Also fix the start address of checked IO region from 0xa0000000 to
the full Region 1 in sysmap.h, and add plic and clint sections like
other RISC-V CPU cores (although they're internal to the CPU and won't
be usable by LiteX).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Provides an alternate API to some functions of the SoCBusHandler and bus
Arbiter classes to allow users of the API to avoid the terms 'master'
and 'slave' in certain situations.
Signed-off-by: Alan Green <alan.green@gmail.com>
Currently the code uses the SoC bus width to calculate the alignment of
CSR banks.
However when we get AXI-Lite interconnect support, the CSR bus is not
directly converted from SoC bus now, instead an intermediate bus with
default parameter (which means 32-bit) is created, CSR bus is converted
from it, and finally this bus is attached to the main interconnect with
auto converter if needed. In this case the intermediate bus is always of
32 bit bus width, eliminating the need of caring the SoC bus width when
handling CSR banks.
Tested on 64-bit SoC bus width now; to make the bus further wider,
other codes need to be changed either.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Currently L1$ flush code does not work well because of lack of
synchorizing.
Switch to use T-Head extended instructions instead of CSRs to flush L1
cache (both D and I), and THEADISAEE is set for this.
In addition, Some other performance-related options are enabled too,
including branch predicting, cache prefetching, etc.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Defines WITH_CXX to the C compiler when including hello.cpp in the demo.
This fixes a bug wahere the the menu did not include the hellocpp item
even when --with-cpp was passed to demo.py
Signed-off-by: Alan Green <alan.green@gmail.com>
We made the bus width of C906 wrong at first, and when we convert its
external interface from AXI-Lite to AXI, it's id width is wrong too.
In addition, the AXI down converter of LiteX is quite weird, so a AXI2WB
bridge is integrated into the core now, like what is done in CVA6.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
The csr opcodes are no longer part of the i instruction set, and must be
enabled separately. This can be done by adding _zicsr to the march
string, eg. -march=rv32i_zicsr. However this is not recognised by older
toolchains, so we can't change over until everyone is using binutils
2.28 or later.
An alternate fix was merged for Vexriscv by patching .S files in
https://github.com/enjoy-digital/litex/pull/1292. This only fixes the
problem for .S files, so the usage of csr instructions in c files was
still broken.
Later it was fixed for all source files for Vexriscv in
https://github.com/enjoy-digital/litex/pull/1321 by telling the compiler
to target the 2.0 ISA, where the csr instructions were still present.
Make the same change to all riscv cpus that specify -march=rv32. This
should allow both old and new toolchains to build software.
Signed-off-by: Joel Stanley <joel@jms.id.au>
As of April 2022, GHDL can output Verilog directly without the use of
yosys. This simplifies the build environment for flows that simply want
to convert VHDL to Verilog.
Note that this removes some arguments from ghdl that are not required to
synthesise ether Microwatt or neorv32.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Florent Kermarrec
Gwenhael Goavec-Merou
Joel Stanley
Icenowy Zheng
Alan Green
Christian Klarhorst