9f0a03100d
litex_setup: Add more comment, fix checkout when sha1 starting with 0.
2021-10-07 19:03:29 +02:00
1629bcbf30
Merge pull request #1058 from gsomlo/gls-rocket-smp-ecp5
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cpu/rocket: add dual-core (smp) variants
2021-10-07 09:04:08 -04:00
18bd8f3770
cpu/rocket: add dual-core (smp) variants
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- 2-core "linux" (fpu-less) variants with double, quad mem. bus width
2021-10-06 08:48:27 -04:00
f03a15820b
tools/litex_sim: Remove useless pre_run_callback toolchain attribute.
2021-10-06 09:16:08 +02:00
04885a5d77
Merge pull request #1057 from antmicro/rocket-asm-alignment
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cpu/rocket: naturally align data defined in crt0.S
2021-10-04 17:57:43 +02:00
99f3498f2d
cores/icap/ICAP: Add Register read capability.
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Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
2021-10-04 17:22:57 +02:00
771897fa37
cpu/rocket: naturally align data defined in crt0.S
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The startup code accesses this data using sd/ld instructions, which
require that the address being accessed is 8-byte aligned.
The .dword asm directive does NOT imply any alignment, so we need
to force it using the .align directive.
2021-10-04 15:22:13 +02:00
3504904c09
cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend).
2021-10-04 15:06:03 +02:00
9416e30249
test/test_icap: Add IPROG sequence check.
2021-10-04 14:41:38 +02:00
cb2f2d7021
cores/icap/ICAP: Rewrite using constants and cleanup.
2021-10-04 14:25:40 +02:00
1f2b143c66
cores/icap: Add Configuration Registers and Commands definition.
2021-10-04 13:35:36 +02:00
6b3b243bb3
cores/icap: Fix/Update comment.
2021-10-04 11:37:40 +02:00
cb6861e1c8
build: Add initial/minimal QuickLogic build support.
2021-10-01 11:42:56 +02:00
16702c44fe
Merge pull request #1055 from gsomlo/gls-pico-warn-64
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64-bit follow-up for picolibc warning fixes
2021-10-01 10:49:07 +02:00
d92f10dfb0
64-bit follow-up for picolibc warning fixes
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Providing "uint32_t" to printf's "%ld" results in warnings on 64-bit
builds: use "unsigned long" instead.
2021-09-30 20:26:40 -04:00
77283d3d8d
software: Fix picolibc compilation warnings.
2021-09-30 19:24:58 +02:00
841732f38f
software/liblitesata: Fix compilation with picolibc.
2021-09-30 18:56:01 +02:00
7b7fd25d5d
Merge pull request #1054 from niw/fix_disk_read_arg_name
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FIX: arg name is changed.
2021-09-30 17:44:33 +02:00
abcf5f1d7b
FIX: arg name is changed.
2021-09-30 02:56:19 -07:00
47e4a1b437
tools/litex_term: Avoid staying in safe mode on next upload when previous calibration failed.
2021-09-30 10:11:48 +02:00
4563ccae18
Merge pull request #1052 from developandplay/patch-5
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Add ninja to toolchain setup
2021-09-30 09:33:28 +02:00
5e2d03dad7
Add ninja to toolchain setup
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In addition to meson I had to install ninja for the picolibc update.
Not sure if it was just an issue on my system but wanted to flag it.
2021-09-30 00:10:45 +02:00
5661480409
tools/litex_term: Add automatic inter-frame delay calibration and --safe mode.
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By default, litex_term will now automatically try to find the best inter-frame delay/payload length
parameters to optimize upload speed. The --safe mode can also be used to disable outstanding frames
(and then wait ack for each frame), it will be slow on regular UARTs (that have high round-trip
latencis) but should always work.
2021-09-29 18:41:06 +02:00
80cb53fb04
software/bios/boot: Allow frame reception to time out during serial boot and do some cleanup/add comments.
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Allowing the serial boot to time out during frame reception allows doing test on the Host side to
calibrate the minimum inter-frame delay and maximum payload length.
In the future, we should probably compute the CRC directly during frame reception and do the mempcpy
of frame N during the reception of frame N+1 to avoid these inter-frame constraints.
2021-09-29 18:33:59 +02:00
5a35aa9df6
software/libliteeth: Fix missing prototype warnings.
2021-09-28 17:46:23 +02:00
7bf6db5f9d
README: Add meson package install.
2021-09-28 16:27:30 +02:00
9a931324c2
get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.
2021-09-28 16:27:13 +02:00
a5b3ab1bc9
Merge pull request #1051 from antmicro/picolibc-updates
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Picolibc updates
2021-09-28 16:01:29 +02:00
9f1108c2fc
libc: refactor picolibc build deps
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:30 +02:00
b9c4d7ba51
libc: add _impure_ptr definition
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:08 +02:00
22f50ec7ff
libc: add errno include
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This solves missing `__errno` symbol linker errors
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:16:34 +02:00
a588c3b830
software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket).
2021-09-28 14:51:02 +02:00
99d8bbc3bc
Merge pull request #1050 from antmicro/fix-litex_setup_url
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Revert litex_setup_url change
2021-09-28 14:28:29 +02:00
061b89beff
cpu/picolibc: Add family property to CPUs and directly use it for picolibc.
2021-09-28 14:20:13 +02:00
b451f102c6
software/libc/stdio: Simplify/Cleanup.
2021-09-28 14:04:24 +02:00
12c93ea895
litex_sim: Generate gtkw_savefile only with --trace.
2021-09-28 13:32:12 +02:00
c0e7e3acd3
Revert litex_setup_url change
2021-09-28 12:35:20 +02:00
782744bae3
tools/litex_sim/generate_gtkw_savefile: Check main_ram presence.
2021-09-28 10:02:17 +02:00
de738e153d
tools/litex_sim: Avoid double build iteration with pre_run_callback function.
2021-09-28 09:58:43 +02:00
c98c777bed
integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups.
2021-09-28 08:57:49 +02:00
29fb1c48d0
Merge pull request #1046 from antmicro/libc-deps
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software: libc: fix Makefile dependecies
2021-09-27 14:56:25 -07:00
d101ef7ed0
software: libc: fix Makefile dependecies
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-27 23:05:54 +02:00
01a906add7
software/liblitesdcard: Fix compilation with picolibc.
2021-09-27 18:56:18 +02:00
727d898a6c
software/libliteeth: Update/Fix compilation with picolibc.
2021-09-27 18:54:28 +02:00
54623dbe26
litex_setup: Update picolibc url (now on litex-hub).
2021-09-27 18:15:10 +02:00
7119dd8098
Merge pull request #1023 from lschuermann/dev/litex-sim-gmii-xgmii
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litex_sim: add support for simulated GMII & XGMII, rewrite XGMII module
2021-09-27 17:48:44 +02:00
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii
2021-09-27 17:47:26 +02:00
9ab82cacda
soc/add_ethernet/etherbone: Fix conflicts/Update.
2021-09-27 17:43:39 +02:00
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter
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cpu/rocket/core: Remove ResetInserter on adapters.
2021-09-27 16:34:46 +02:00
49f8652f91
ci: Install meson (now required by picolibc).
2021-09-27 16:19:56 +02:00
Florent Kermarrec
gsomlo
Jakub Piecuch
Yoshimasa Niwa
developandplay
Karol Gugala
Michal Sieron
Tim Ansell