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833 Commits 40 Branches 14 Tags 51 MiB
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833 Commits

Author SHA1 Message Date
Florent Kermarrec 8a2b65f21d continue code refactoring 2015-01-28 09:28:33 +01:00
Florent Kermarrec 4cd73fc9da change name to LiteEth (LiteEthernet is too long...) 2015-01-28 01:36:38 +01:00
Florent Kermarrec 8477974ef1 start code adaptation 2015-01-28 00:51:31 +01:00
Florent Kermarrec 0826811047 etherbone: import core from Robert Jordens 2015-01-28 00:10:26 +01:00
Florent Kermarrec 46c4841d68 mac: import files from MiSoC 2015-01-27 23:59:06 +01:00
Florent Kermarrec a160b04d2f init repo 2015-01-27 23:50:52 +01:00
Florent Kermarrec 9bb7e6d0ab ethmac: improve testbenchs 2014-12-21 17:37:25 +08:00
Florent Kermarrec ceb675c3f1 fix cf92821 merge issue 2014-12-19 21:49:49 +08:00
Sebastien Bourdeauducq aac34f011f gensoc: support user-defined CSR regions 2014-11-30 22:29:26 +08:00
Sebastien Bourdeauducq 8ae3a00a94 gensoc: simplify WB address decoding 2014-11-30 22:05:51 +08:00
Sebastien Bourdeauducq 4189440eef minicon: small simplifications 2014-11-28 08:28:39 +08:00
Yann Sionneau edb1622668 spiflash: BB write support 2014-11-27 23:10:39 +08:00
Sebastien Bourdeauducq bab6bb7c4a gensoc: fix align 2014-11-27 23:05:36 +08:00
Sebastien Bourdeauducq 2cd80990e4 minicon: fix use of phy phases 2014-11-27 22:13:17 +08:00
Sebastien Bourdeauducq 8418ccafdc minicon: remove unused signals and fix indent 2014-11-27 22:12:05 +08:00
Yann Sionneau cf92821fcf Refactor directory hierarchy of sdram phys and controllers 2014-11-27 22:09:10 +08:00
Yann Sionneau f33b285af1 Minicon: small SDRAM controller 2014-11-27 22:09:03 +08:00
Florent Kermarrec 5202f89db1 ethmac/last_be: remove fake signal (fixed in Migen) 2014-11-21 14:48:17 -08:00
Sebastien Bourdeauducq b7028848b2 ethmac: use new EndpointDescription API 2014-11-20 22:32:32 -08:00
Sebastien Bourdeauducq 33530e0921 ethmac: style/renaming 2014-11-20 18:01:48 -08:00
Sebastien Bourdeauducq 7eaa5f7372 targets/kc705: avoid ddrphy/ethphy address conflict 2014-11-20 17:11:57 -08:00
Florent Kermarec 603c2641bb new Ethernet MAC 2014-11-20 16:47:22 -08:00
Sebastien Bourdeauducq f4d6ac8393 README: remove compiler-rt download instructions 2014-11-06 18:02:02 -08:00
Sebastien Bourdeauducq 09773df186 software: make compiler-rt a submodule 2014-11-06 18:00:28 -08:00
Florent Kermarrec 8e4b89849c use new direct access on endpoints 2014-10-20 23:13:37 +08:00
Florent Kermarrec 34ed315a48 remove trailing whitespaces 2014-10-17 17:14:40 +08:00
Sebastien Bourdeauducq 20528c622a mor1kx: sync 2014-10-10 15:38:05 +08:00
Sebastien Bourdeauducq e53fb88b85 uart: minor cleanup and fix 2014-10-10 15:33:27 +08:00
Florent Kermarrec 5e5f436aa6 uart: split it and use dataflow 
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
 2014-10-10 15:24:47 +08:00
Florent Kermarrec c1fc0b9c97 update README with new Kintex-7 support 2014-09-26 10:36:29 +08:00
Florent Kermarrec 13fb9282db targets: add simple design (vendor agnostic and usable on all platforms with UART pins). 
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
 2014-09-26 10:35:15 +08:00
Sebastien Bourdeauducq 410f250d2a software: remove setjmp 2014-09-23 21:57:05 +08:00
Sebastien Bourdeauducq 14d53526be libbase: use __builtin_setjmp and __builtin_longjmp 2014-09-21 17:43:17 +08:00
Sebastien Bourdeauducq 503a2f00b5 mor1kx: sync 2014-09-12 16:00:32 +08:00
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 36434b62f0 sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE 2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq 2388bfabc3 bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 14:25:26 +08:00
Sebastien Bourdeauducq a7b4550e59 sdramphy/initsequence: cleanup and expose DDR3 MR1 value 2014-09-03 14:21:30 +08:00
Florent Kermarrec 114890ee80 sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT 2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq 2234f50223 k7ddrphy: add bitslip control for incoming DQ 2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq 0eeb0ad9eb targets/kc705: add ddrphy to CSR map 2014-09-01 16:40:10 +08:00
Sebastien Bourdeauducq 6decb357f1 bios: add sdrrderr 2014-09-01 15:23:37 +08:00
Sebastien Bourdeauducq 57335bdf3f bios: add DQ filtering to sdrrd, add sdrrdbuf command 2014-09-01 14:58:58 +08:00
Sebastien Bourdeauducq 5483b37c8f k7ddrphy: write leveling and read calibration support 2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq 19abe2b888 k7ddrphy: do not register T at SERDES (fixes timing problem) 2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq a2096ff083 libcompiler-rt: add moddi3 2014-08-28 16:54:12 +08:00
Sebastien Bourdeauducq 541e5abbc7 k7ddrphy: update comment 2014-08-22 19:02:57 +08:00
Sebastien Bourdeauducq 66fe45ba96 k7ddrphy: decrease CAS latency to account for cmd/data flight time 2014-08-22 18:46:01 +08:00
Sebastien Bourdeauducq b94647ab16 k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter 2014-08-22 18:45:25 +08:00
Sebastien Bourdeauducq 35327a427f targets/kc705: BIOS XIP 2014-08-22 17:13:10 +08:00