9d5bf70cb2
cpu/femtorv/firev: Remove debug displays now that validated in sim and hardware.
2022-03-09 10:54:05 +01:00
ece286b15d
litex_setup: Rename --status to --freeze and generate freezed git_repos dict.
2022-03-08 18:12:11 +01:00
7411109f4d
gowin/programmer: Fix copyright year.
2022-03-08 17:25:27 +01:00
72576c87fc
Merge pull request #1234 from curliph/master
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for windows/(powershell and WSL) support
2022-03-08 17:23:05 +01:00
700077e4a1
powershell and WSL support
2022-03-08 13:52:03 +08:00
cfab857c7b
win/powershell support.
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add gowin programmer support.
2022-03-08 13:16:01 +08:00
7ebc7625d5
tools/litex_client: Add --csr-csv support.
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Useful to debug multi-FPGA projects.
2022-03-07 11:42:32 +01:00
87d5d7c87c
cpu/firev/core: Review/Cleanup pass, also fix set_reset_address.
2022-03-04 12:12:06 +01:00
ea883909b5
Merge pull request #1232 from sylefeb/silice-firev
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Silice FireV
2022-03-04 11:41:13 +01:00
8ade60a55d
soc/reset: Change the way crg_rst is set to allow possible multiple assignation in the code.
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This allows user's cores to also exercise the CRG rst with code similar to:
self.comb += If(<rst_condition>, self.crg.rst.eq(1))
2022-03-04 10:47:52 +01:00
2d40846c34
Merge branch 'enjoy-digital:master' into silice-firev
2022-03-03 21:41:21 +01:00
7fcecf437a
Merge pull request #1230 from antmicro/add-cpus-to-litex_json2renode
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Add CPUs to litex_json2renode script
2022-03-03 17:33:43 +01:00
b092d2a180
cores/jtag: Fix chain parameter on XilinxJTAG.
2022-03-03 16:45:20 +01:00
e00eafd97f
cores/ram: Add Xilinx Ultrascale+ HBM2 wrapper.
2022-03-03 16:33:05 +01:00
f5f0937493
added firev CPU
2022-03-03 15:07:38 +01:00
c3fb321532
tools/litex_json2renode: Add support for Minerva
2022-03-03 12:04:33 +01:00
d86bdb71ec
tools/litex_json2renode: Don't use generic RV32 for Ibex
2022-03-03 12:03:03 +01:00
35dd5554ba
tools/litex_json2renode: Add cv32e40p support
2022-03-03 11:59:26 +01:00
46361db135
Merge pull request #1229 from smunaut/jtag-zynq-usp
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cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
2022-03-02 21:56:03 +01:00
d8df6cb27d
cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-02 14:12:18 +01:00
4bc1691487
soc/cores/xadc: Update copyrights.
2022-03-01 14:48:02 +01:00
0a40616df9
litex_setup.py: Remove LiteHyperBus dependency (not currently used by LiteX-Boards).
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We could add it back as a dependency if the simple/portable core is no longer enough for
regular use cases.
2022-03-01 09:27:23 +01:00
dbde036162
soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
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The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
2022-03-01 09:11:55 +01:00
6c93db0f14
Merge pull request #1228 from sergachev/master
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Minor fixes
2022-02-28 11:01:02 +01:00
6e87827ce2
integration/soc: fix inexistent word "supporteds"
2022-02-26 10:41:14 +01:00
54bed133f4
build/tools: add .vp encrypted verilog file extension awareness
2022-02-26 10:38:11 +01:00
7f49c5235e
core/video: Update copyrights.
2022-02-25 11:28:09 +01:00
89f19ea510
Merge pull request #1226 from smunaut/sysmon
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cores/xadc: Improve support for Zynq Ultrascale+
2022-02-25 10:39:40 +01:00
22886f3465
Merge pull request #1227 from fjullien/fix_video
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Fix video (vtg and colorbars)
2022-02-25 10:38:46 +01:00
a916a1df24
video:ColorBars: fix for hres not divisible by 8
2022-02-25 09:26:22 +01:00
ced763e3d9
video:vtg: fix off by one error in hscan and vscan
2022-02-25 09:26:22 +01:00
8f00b0f182
cores/xadc: Improve support for Zynq Ultrascale+
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Although for 'standard' UltraScale+ just letting Vivado upgrade
SYSMONE1 to SYSMONE4 works, it doesn't for the Zynq because the
default SIM_DEVICE not matching up creates a fatal DRC when
creating bitstream.
So instead we add separate classes for UltraScale, UltraScale+ and
Zynq UltraScale+, each instanciating the right blocks, with the
right params. Also we only create the VCCPSINTLP//VCCPSINTFP/VCCPSAUX
for the Zynq UltraScale+.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-02-25 09:21:19 +01:00
b54384ca73
Merge pull request #1225 from fjullien/efinix_dbparser
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efinix:dbparser: add get_pad_name_from_pin and use it
2022-02-24 22:29:54 +01:00
8303e462ec
Merge pull request #1224 from fjullien/fix_add_sources
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platform: fix add_sources
2022-02-24 22:29:18 +01:00
b77fb9f6a1
Merge pull request #1223 from fjullien/efinix_add_mipi_tx_block
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efinix: add MIPI TX block
2022-02-24 22:27:51 +01:00
97d1ae0fc2
Merge pull request #1222 from fjullien/efinix_implement_fix_xml
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efinix: add a list of values to fix in xml
2022-02-24 22:26:23 +01:00
9c01eff5fa
Merge pull request #1221 from fjullien/efinix_implement_phase_shift_pll_v3
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efinix: implement pll v3 phase shift
2022-02-24 22:24:31 +01:00
e15cd66762
efinix: implement pll v3 phase shift
2022-02-24 21:40:53 +01:00
1b22c6c0ad
efinix: add a list of values to fix in xml
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Sometimes the Python API of the interface designer produce a wrong XML
file. Values can be changed in the XML file with this new list.
For example:
fix_pll = [
# Tag name properties / values
("comp_output_clock", "mipi_clk", [("out_divider", "20")]),
("comp_output_clock", "mipi_tx_clk_fastclk", [("out_divider", "4"), ("phase_setting", "3")]),
("comp_output_clock", "mipi_tx_data_fastclk", [("out_divider", "4"), ("phase_setting", "1")]),
("comp_output_clock", "mipi_tx_slowclk", [("out_divider", "16")])
]
platform.toolchain.ifacewriter.fix_xml += fix_pll
2022-02-24 21:40:17 +01:00
77e55978d8
efinix: add MIPI TX block
2022-02-24 21:38:26 +01:00
289c7fbf54
platform: fix add_sources
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If the Builder class is not used to build the projet, platform sources
is still a list of tupples with 4 elements.
For now, we don't handle file copy when Builder is not used but at least
it won't crash.
2022-02-24 21:24:05 +01:00
9de86c84d6
efinix:dbparser: add get_pad_name_from_pin and use it
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get_gpio_instance_from_pin returned the pad name.
It now returns the gpio block name.
To get the pad name, there is now get_pad_name_from_pin.
2022-02-24 21:11:40 +01:00
f6d6611a81
software/liblitedram: Introduce SDRAM_PHY_DELAY_JUMP and set to 4 on 7-Series instead of 1 to improve calibration robustness on some boards.
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This is for example required on the STLV7325 board.
2022-02-24 17:32:58 +01:00
82daa48e09
software/bios/libbase: Always do memtest/memspeed when main_ram is present.
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- Enable memtest/memspeed on design with HyperRAM.
- Allow comparisons between SDRAM/HyperRAM and integrated RAM.
2022-02-23 10:19:20 +01:00
4acbafbc19
cpu/naxriscv allow reset_vector >= 0x80000000
2022-02-22 12:21:05 +01:00
038b66bae5
cpu/naxriscv add reset vector support
2022-02-22 11:06:02 +01:00
cd57202e5e
cpu/NaxRiscv fix for windows
2022-02-22 10:37:22 +01:00
1b62f14230
build: Add initial OpenFPGA build backend with SOFA support and minimal blinky example.
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OpenFPGA should be installed by following installation steps from https://github.com/lnis-uofu/OpenFPGA .
SOFA can be cloned from https://github.com/lnis-uofu/SOFA
Environment variables then need to be set:
export LITEX_ENV_OPENFPGA=/PATH_TO_OPENFPGA
export LITEX_ENV_OPENFPGA_SOFA=/PATH_TO_SOFA
A simple blinky test design is provided and can be built by executing blinky.py.
2022-02-21 17:07:39 +01:00
8559b88ad8
build/efinix/platform: Transform Slices until we get target Signal (fixes SDCard SD-mode on TI62-F225).
2022-02-21 10:34:09 +01:00
d2a2c2e5dc
cpu/naxriscv update nax
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fix sbt version
2022-02-20 22:31:04 +01:00
Florent Kermarrec
curliph
sylefeb
Sylvain Lefebvre
Michal Sieron
Sylvain Munaut
Ilia Sergachev
Franck Jullien
Dolu1990