a0853d15ca
Merge pull request #1251 from motec-research/field_size
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export: fix mask for field size 31
2022-03-25 09:35:51 +01:00
d9e39d64b3
export: fix mask for field size 31
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software/include/generated/csr.h:110:2: warning: integer overflow in expression '-2147483648 - 1' of type 'int' results in '2147483647' [-Woverflow]
uint32_t mask = ((1 << 31)-1);
^~~~~~~~
2022-03-25 09:19:16 +11:00
0bd2abf68d
Merge pull request #1250 from pftbest/connect_to_pads_last
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Fix missing "last" pin connection when using connect_to_pads
2022-03-24 14:46:25 +01:00
967ea12364
cpu/vexriscv_smp: Fix pbus data-width (Max of icache/dcache-width).
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Fix boot with > 1 CPU or with FPU when using --with-wishbone-memory.
2022-03-24 14:34:38 +01:00
0ac3d677b5
bios/main: Test Main RAM only when not pre-initialized (corrupt contents otherwise).
2022-03-24 14:34:29 +01:00
d3f3f658cb
integration/soc: Generate RAM_INIT config defined when ram is initialized.
2022-03-24 14:34:26 +01:00
c1898b9355
Fix missing "last" pin connection when using connect_to_pads
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When using connect_to_pads on full AXI interface the "last" pin was not connected because of this typo.
2022-03-24 15:37:59 +04:00
ef6d450820
Merge pull request #1249 from enjoy-digital/setup_fix
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Fix litex_setup.py and use local version on CI.
2022-03-24 10:59:44 +01:00
caced992ad
litex_setup: Remove pip3 install amaranth-yosys.
2022-03-24 10:33:10 +01:00
1935a2599f
workflows/ci: Use local version of litex_setup.
2022-03-24 10:17:08 +01:00
72b61155c7
workflows/ci: Checkout to /usr/litex.
2022-03-24 10:12:38 +01:00
41bd8539c3
setup.py: Remove migen/pythondata-software-compiler-rt (Installed through litex_setup.py).
2022-03-24 10:06:31 +01:00
a3b62c9b95
Merge pull request #1248 from motec-research/pip_install
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litex_setup: change to installing with pip
2022-03-24 09:53:17 +01:00
3f72cd30b1
litex_setup: change to installing with pip
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fixes: EasyInstallDeprecationWarning: easy_install command is deprecated. Use build and pip and other standards-based tools.
2022-03-23 11:22:56 +11:00
dd7a04a5c0
liblitedram/sdram_leveling_center_module: Do a check after final delay configuration.
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On ECP5/DDR3, final configuration does not seem to be done correctly each time.
Add a retry/check mechanism to workaround the issue for now.
2022-03-22 17:12:50 +01:00
153f9f3660
soc_core: Fix l2_size argument handling.
2022-03-22 11:23:01 +01:00
f0bd7019cd
soc/add_jtagbone/add_sdram: Add/Use name parameter.
2022-03-22 09:53:48 +01:00
e227f3b038
soc: Improve logs on add_controller, add_csr_bridge and add_cpu.
2022-03-22 09:41:20 +01:00
33d6c3de8f
builder/soc_core: Add missing title.
2022-03-21 18:07:34 +01:00
901428f5a9
soc/add_ethernet: Fix add_ethernet.
2022-03-21 18:03:40 +01:00
be23a059ff
soc/interconnect/csr/CSRConstant: Add constant attribute.
2022-03-21 18:03:15 +01:00
4a5ce77d40
build/soc/cpu parser: Improve titles.
2022-03-21 17:53:30 +01:00
1e6e9777e2
Merge pull request #1245 from developandplay/demo-fix
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Fix compilation of demo.bin on Rocket
2022-03-21 17:15:59 +01:00
1583cc8a40
cpu/naxriscv: Add default value to xlen argument.
2022-03-21 17:14:24 +01:00
8e440dc9ea
soc/integration: Add LiteXSocArgumentParser to be able to expose CPU parameters to user on targets.
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Currently used for CPU parameters could problably be extented to simplify other parts
of the code in the future.
2022-03-21 16:57:14 +01:00
6ef96b17bc
soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
2022-03-21 15:21:08 +01:00
f5d4977dde
Merge pull request #1246 from gsomlo/gls-memtest-cast-warning
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bios/memtest: fix cast warning
2022-03-20 21:09:36 +01:00
e5a2305269
bios/memtest: fix cast warning
2022-03-20 14:30:16 -04:00
884ee45c28
Fix compilation of demo.bin on Rocket
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- Adjust memory model to fix `relocation truncated` errors
- Make isr.c shared between BIOS and demo to resolve dep on `plic_init`
Based on: https://github.com/enjoy-digital/litex/issues/1168
2022-03-20 15:39:13 +01:00
f565bec7f1
cpu/naxriscv fix xlen not being hashed, improve RV64 performances
2022-03-18 15:39:58 +01:00
58549834ec
tools/litex_sim: Use new get_boot_address function.
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Allow litex_sim to use similar .json files than the ones used on hardware.
2022-03-17 17:46:27 +01:00
4036c75600
integration/common: Add get_boot_address to get CPU boot address from json file.
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Will allow litex_sim to use similar .json files than the ones used on hardware.
2022-03-17 17:45:30 +01:00
dd7709ed6f
tools/litex_sim/add_sdram: origin no longer required.
2022-03-17 16:47:02 +01:00
05724d9fea
cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents.
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Avoid doing it in Linux-on-LiteX-Vexriscv.
2022-03-17 16:28:25 +01:00
b4db2a3ef2
tools/litex_sim: Remove obsolete max_sdram_size parameter.
2022-03-17 16:14:26 +01:00
3b4a885366
cpu/naxriscv/vexriscv_smp: Also enforce UART/Timer0 IRQs.
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Avoid doing it in Linux-on-LiteX-Vexriscv and allow generating bitstreams directly from litex-boards.
2022-03-17 16:10:34 +01:00
e6e3a909f2
cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility.
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This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards.
2022-03-17 16:00:05 +01:00
2ec0ebe40f
build/gowin: Add copy of bitstream to from impl to gateware directory.
2022-03-17 09:35:34 +01:00
148324862a
integration/builder: Add get_bios_filename/get_bitstream_filename methods to simplify targets/projects.
2022-03-17 09:19:41 +01:00
e6a81ec2af
integration/soc/add_etherbone: Set default buffer_depth to 16 (Allow LiteScope's width up to 512-bit).
2022-03-16 16:43:28 +01:00
371608712f
litex_client: Add CSR Filter.
2022-03-16 10:59:47 +01:00
488a6d7256
litex_client/gui: Minor changes.
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- By default, always on top.
- Update register on enter.
- Add title to viewport.
2022-03-16 09:39:04 +01:00
1b128804ae
tools/litex_client: Add initial and very simple GUI support.
2022-03-15 19:19:01 +01:00
4896527e6f
cpu/naxriscv fix git and add RV64 support (--xlen 64)
2022-03-15 11:54:28 +01:00
7712c8a79f
Merge pull request #1236 from gregdavill/trellis_compress_default
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build/trelis: Compress bitstream by default
2022-03-11 21:56:41 +01:00
43cc2ff9bb
software/libbase/memtest: Skip memtest_addr when size < 16KB.
2022-03-11 15:28:34 +01:00
c851e74e09
README: Add link to new LiteX quick tour/overview presentation.
2022-03-10 18:13:44 +01:00
1ebcc03a92
soc/add_pcie: Add address_width support for 64-bit addressing.
2022-03-10 16:09:18 +01:00
3de88c1aed
build/trelis: Compress bitstream by default
2022-03-10 13:51:14 +10:30
f446415f68
cpu/minerva: nMigen -> Amaranth.
2022-03-09 11:00:50 +01:00
enjoy-digital
Andrew Dennison
Vadzim Dambrouski
Dolu1990
Gabriel Somlo
developandplay
Greg Davill