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Author SHA1 Message Date
Lars-Peter Clausen 72579a6129 Add support for negative slice indices 
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq c99cc9343f examples/pytholite: use new APIs 2013-03-12 16:59:24 +01:00
Sebastien Bourdeauducq 69dbf84e54 sim/generic: support implicit get_fragment 2013-03-12 16:54:01 +01:00
Sebastien Bourdeauducq d92ca43cd0 vpi: make it work by default on Arch 2013-03-12 16:51:58 +01:00
Sebastien Bourdeauducq 907bfa87f4 examples/basic: use new APIs 2013-03-12 16:45:28 +01:00
Sebastien Bourdeauducq ecfe1646ec fhdl/verilog: implicit get_fragment 2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq c06a821452 generic_platform: implicit get_fragment 2013-03-12 16:14:13 +01:00
Sebastien Bourdeauducq 1e7783a41e build.py: use implicit get_fragment 2013-03-12 16:13:20 +01:00
Sebastien Bourdeauducq 4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq a23df42a7a Use automatic register naming 2013-03-12 15:47:54 +01:00
Sebastien Bourdeauducq 04df076fba bank: automatic register naming 2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq 7e2581bf17 fhdl/tracer: recognize CALL_FUNCTION_VAR opcode 2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq 12158ceadf fhdl/tracer: recognize LOAD_DEREF opcode 2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq 3c75121783 fhdl/tracer: remove leading underscores from names 2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq c4d9734e53 README: update 2013-03-11 20:29:47 +01:00
Florent Kermarrec 60e2cdfe79 get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection 2013-03-11 20:05:30 +01:00
Sebastien Bourdeauducq 80970b203c bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq b042757187 Fix Register name conflict between Pytholite and Bank 2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq a9b723568a Use new module, autoreg and eventmanager Migen APIs 2013-03-10 19:32:38 +01:00
Sebastien Bourdeauducq f93695f60e bank/eventmanager: use module and autoreg 2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq 174e8cb8d6 bus/asmibus: use fhdl.module API 2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq 17e0dfe120 fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq cddbc1157d bank/description/AutoReg: check that get_memories and get_registers are callable 2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq 68fe4c269c bank/csrgen: BankArray 2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq f1474420df bank/description: AutoReg 2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq d0676e2dd1 migen/fhdl/autofragment: factorize 2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq d0d2df3c4b fhdl/autofragment: remove legacy functions 2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq 72fb6fd6bd fhdl/tools/flat_iteration: generalize 2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq f53acb92e7 fhdl/autofragment: fix submodules 2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq 6da8eb906f fhdl/autofragment: empty build_fragment by default 2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq 2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq b75fb7f97c csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
Sebastien Bourdeauducq 6fa30053bf fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq 2059592db2 software/libcompiler-rt: add ctzsi2 2013-03-06 11:10:16 +01:00
Sebastien Bourdeauducq 4d4d6c1f88 platforms/m1: add video mixer extension board 2013-03-05 23:03:01 +01:00
Sebastien Bourdeauducq 9b4ca987e0 bus/csr: support memories with larger word width than the bus (read only) 2013-03-03 19:27:13 +01:00
Sebastien Bourdeauducq bb5ee8d3bd fhdl/autofragment: bugfixes + add auto_attr 2013-03-03 17:53:06 +01:00
Sebastien Bourdeauducq cc8118d35c fhdl/autofragment: FModule 2013-03-02 23:30:54 +01:00
Sebastien Bourdeauducq d2491828a4 csr/SRAM: prefix page register with memory name 2013-03-01 12:06:12 +01:00
Sebastien Bourdeauducq 6a412f796e xilinx_ise: add lock cycle to bitgen 2013-03-01 11:29:40 +01:00
Florent Kermarrec edce543b14 adapt to migen changes 2013-03-01 01:09:00 +01:00
Florent Kermarrec 80e9db7e61 use mibuild for de1 example 2013-02-28 23:11:41 +01:00
Florent Kermarrec 58a6acba27 use mibuild for de0_nano example 2013-02-28 23:02:06 +01:00
Florent Kermarrec 58edd7632c compiles but untested 2013-02-28 00:32:42 +01:00
Sebastien Bourdeauducq c10622f5e2 fhdl/verilog: insert reset before listing signals 2013-02-27 18:10:04 +01:00
Florent Kermarrec 5accd48a17 doc: update 2013-02-26 23:45:01 +01:00
Florent Kermarrec 87336128a3 sim: update 2013-02-26 23:25:10 +01:00
Florent Kermarrec ae900c9c16 examples: use miscope.bridges 2013-02-26 23:20:29 +01:00
Florent Kermarrec 5fc89f0c71 move spi2csr to briges/spi2csr 2013-02-26 23:17:34 +01:00
Florent Kermarrec f823d06cf1 examples: update & simplify 2013-02-26 23:14:09 +01:00