ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
3575d03faa
.travis.yml: disable windows test (failing for now).
2020-04-07 12:43:29 +02:00
2ca853fd74
README.md: update RISCV toolchain installation.
2020-04-07 12:39:52 +02:00
d770bfbf2e
.travis.yml: remove Python3.5 test.
2020-04-07 12:33:56 +02:00
bc26af0d47
Merge pull request #451 from mithro/multi-os
...
Add multiple Python versions, Windows and Mac to Travis CI testing
2020-04-07 12:29:04 +02:00
30d25ffe5b
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
...
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:48:16 +02:00
3f1159fa0b
litex_setup: reorganize a bit, add separators/comments.
2020-04-07 11:05:36 +02:00
926f961bf3
.travis.yml: revert full url for litex_setup.py.
...
We want to have an almost identical .travis.yml between LiteX and the Cores.
Using $TRAVIS_BUILD_DIR works for LiteX but will not work for the cores.
2020-04-07 10:55:58 +02:00
447e8d948c
Merge pull request #452 from mithro/riscv-download
...
Add GCC downloading via litex_setup.py
2020-04-07 10:51:27 +02:00
3305a65b77
Enable testing on multiple Python versions.
...
Makes sure LiteX tests pass on all supported Python versions.
2020-04-06 17:58:12 -07:00
6bd5eae43f
Enable CI for Windows and Mac.
2020-04-06 17:58:12 -07:00
9e324d9e16
Remove symlinking step.
2020-04-06 17:57:32 -07:00
7f0ecddfb2
Use shutil.unpack_archive.
2020-04-06 17:45:55 -07:00
a1dd8fc883
Ignore SSL errors on CI.
2020-04-06 17:36:09 -07:00
2b2aff1274
Improve the path messages a little.
2020-04-06 17:27:24 -07:00
141644d157
Make travis use litex_setup.py for GCC download.
2020-04-06 17:16:55 -07:00
6adabae730
Adding SiFive RISC-V toolchain downloading to litex_setup.py
2020-04-06 16:51:14 -07:00
59b7db63b1
Fix alignments.
2020-04-06 16:51:14 -07:00
e408fb8f08
Merge pull request #450 from mithro/litex-setup-fix
...
litex_setup: Use subprocess so failures are noticed.
2020-04-06 23:04:47 +02:00
d781bf2088
Run `litex_setup.py` outside the git clone directory.
...
Otherwise it tries to overwrite the litex directory by cloning LiteX
into it.
2020-04-06 11:38:23 -07:00
dd59dac571
litex_setup: Use subprocess so failures are noticed.
...
os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.
2020-04-06 11:27:40 -07:00
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
cf1c5d99b3
Merge pull request #448 from kessam/patch-1
...
Fix timing constraints
2020-04-06 11:12:12 +02:00
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
27f00851d0
Merge pull request #447 from antmicro/spi-xip
...
Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
ff04869c62
litex_setup: add litespi core
2020-03-30 13:43:45 +02:00
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
...
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
aeb9411ae1
Merge pull request #441 from gsomlo/gls-spisdcard-fixes
...
SPI SDCard fixes and features
2020-03-28 12:50:17 +01:00
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
...
In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
c6b6dee2e7
software/bios: factor out busy_wait() function
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
540218b2d8
software/libbase/spisdcard: fix width of address parameter
...
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
86eec1a413
Merge pull request #439 from antmicro/fix-compiler-rt
...
Update removed llvm compiler-rt repo
2020-03-26 15:36:39 +01:00
5fa2cc6624
Update removed llvm compiler-rt repo
2020-03-26 10:56:28 +01:00
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
Florent Kermarrec
Tim 'mithro' Ansell
kessam
Piotr Binkowski
Ilya Epifanov
Gabriel Somlo
Kamil Rakoczy