Sebastien Bourdeauducq
|
3a960e9e6a
|
flash_extra: use new programmer
|
2014-08-09 14:39:38 +08:00 |
Sebastien Bourdeauducq
|
a6c55d8dde
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make.py: do not use prog.needs_flash_proxy
|
2014-08-09 14:38:56 +08:00 |
Sebastien Bourdeauducq
|
4d2623a87e
|
mor1kx: sync
|
2014-08-09 14:32:57 +08:00 |
Sebastien Bourdeauducq
|
c61f96588a
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mibuild/programmer: remove unneeded needs_flash_proxy attr
|
2014-08-09 14:28:15 +08:00 |
Sebastien Bourdeauducq
|
c8dd4d2b40
|
k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
Sebastien Bourdeauducq
|
54c63275e0
|
platforms/kc705: remove DDR3 multirank pins
|
2014-08-09 10:56:59 +08:00 |
Sebastien Bourdeauducq
|
60706e4b70
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bus/dfi: add CKE and RESET_N
|
2014-08-09 10:56:08 +08:00 |
Sebastien Bourdeauducq
|
41c8c172b5
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targets/kc705: integrate DDR3
|
2014-08-08 21:58:41 +08:00 |
Sebastien Bourdeauducq
|
0ebdf2be6d
|
bios/sdram: cleanup
|
2014-08-08 21:57:58 +08:00 |
Sebastien Bourdeauducq
|
b61dced909
|
bios/sdram: set ODT and RESET_N through DFII
|
2014-08-08 21:57:42 +08:00 |
Sebastien Bourdeauducq
|
8deadc5760
|
dfii: drive ODT and RESET_N
|
2014-08-08 21:56:35 +08:00 |
Sebastien Bourdeauducq
|
1322c0484b
|
lasmicon: drive ODT and RESET_N
|
2014-08-08 21:55:34 +08:00 |
Sebastien Bourdeauducq
|
0550cbb3ce
|
lasmicon: add CWL to PHY settings
|
2014-08-08 21:55:12 +08:00 |
Sebastien Bourdeauducq
|
777ebb7875
|
sdramphy/gensdrphy: fix rddata_en generation
|
2014-08-08 21:41:07 +08:00 |
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
Sebastien Bourdeauducq
|
5fb221e7d9
|
typo
|
2014-08-06 23:58:09 +08:00 |
Sebastien Bourdeauducq
|
efb2466c7e
|
gensoc: add id for KC705
|
2014-08-06 23:53:51 +08:00 |
Sebastien Bourdeauducq
|
fb48b89bac
|
platforms/kc705: generate clocks for SDRAM
|
2014-08-06 23:53:26 +08:00 |
Sebastien Bourdeauducq
|
7ebf08db5e
|
mibuild/xilinx: connect CE on reset synchronizer FFs
|
2014-08-06 23:51:50 +08:00 |
Sebastien Bourdeauducq
|
b124a98d92
|
genlib: add reset synchronizer
|
2014-08-06 19:38:37 +08:00 |
Sebastien Bourdeauducq
|
ca6d6954c1
|
targets/ppro: use migen reset synchronizer
|
2014-08-06 19:38:11 +08:00 |
Sebastien Bourdeauducq
|
4d382328d5
|
mibuild/xilinx: share more code between ISE and Vivado, use special overrides with Vivado, merge xilinx_tools into xilinx_common
|
2014-08-06 19:26:00 +08:00 |
Florent Kermarrec
|
d1ff43faa7
|
gensoc/cpuif: do not generate access functions for registers > 64 bits
|
2014-08-04 22:38:19 +08:00 |
Florent Kermarrec
|
452a4a76f3
|
use verilog namespace to export mila configuration
|
2014-08-03 17:09:01 +02:00 |
Sebastien Bourdeauducq
|
37968e649b
|
targets/kc705: use PLL for clocking
|
2014-08-03 21:42:39 +08:00 |
Florent Kermarrec
|
6ffed70b59
|
uart2wishbone: disconnect rx line from shared pads when bridge is selected
(avoid CPU crash when we communicate with the bridge)
|
2014-08-03 13:15:56 +02:00 |
Sebastien Bourdeauducq
|
8a7afff30a
|
platforms/kc705: fix speed grade
|
2014-08-03 17:51:44 +08:00 |
Florent Kermarrec
|
f4e6cebab2
|
clean up
|
2014-08-03 11:44:27 +02:00 |
Sebastien Bourdeauducq
|
1a09eb7a19
|
mor1kx: sync
|
2014-08-03 15:57:55 +08:00 |
Sebastien Bourdeauducq
|
8adf6027e1
|
platforms/kc705: add automatic clk200 constraint
|
2014-08-03 15:53:58 +08:00 |
Sebastien Bourdeauducq
|
40dcc8b2aa
|
platforms/kc705: use XC3SProg
|
2014-08-03 15:53:42 +08:00 |
Sebastien Bourdeauducq
|
210cb720c1
|
platforms/kc705: use Vivado by default
|
2014-08-03 15:53:21 +08:00 |
Sebastien Bourdeauducq
|
536a220679
|
mibuild/programmer: fix XC3SProg init
|
2014-08-03 15:52:34 +08:00 |
Sebastien Bourdeauducq
|
61eae462f3
|
README: update
|
2014-08-03 15:48:55 +08:00 |
Sebastien Bourdeauducq
|
f7a7137127
|
targets: add basic KC705
|
2014-08-03 15:48:30 +08:00 |
Sebastien Bourdeauducq
|
213cb43ae5
|
Keep only basic SoC designs in MiSoC
|
2014-08-03 12:30:15 +08:00 |
Florent Kermarrec
|
cd51e78f54
|
storage: use SyncFIFOBuffered to implement fifo in block ram
|
2014-08-02 19:12:03 +02:00 |
Florent Kermarrec
|
a0d0742664
|
mibuild/generic_platform: add recursive parameter to add_source_dir
|
2014-08-02 21:25:51 +08:00 |
Sebastien Bourdeauducq
|
8baa957539
|
genlib/fifo: use synchronous memory read instead of additional register
The latter causes problems with InsertReset
|
2014-08-02 08:52:49 +08:00 |
Florent Kermarrec
|
47a85cc1ad
|
use new MiSoC fifo (no flush signal)
|
2014-08-01 10:36:15 +02:00 |
Sebastien Bourdeauducq
|
9395214d75
|
remove stale programmer.py
|
2014-08-01 12:34:38 +08:00 |
Florent Kermarrec
|
62c9043d07
|
move programmer to mibuild
|
2014-08-01 08:03:53 +08:00 |
Florent Kermarrec
|
82068267db
|
mibuild: move programmer to mibuild and create programmer directly in platforms
|
2014-08-01 08:03:36 +08:00 |
Florent Kermarrec
|
25b3aff6f1
|
sdramphy: add init sequence for DDR3
|
2014-07-31 10:29:32 +08:00 |
Yann Sionneau
|
32171da46d
|
Better UART baudrate generator, and testbench
This enables high speed (tested to 4Mbps) operation.
|
2014-07-31 10:24:52 +08:00 |
Sebastien Bourdeauducq
|
244ee52381
|
kc705/ddram: use lighter pin syntax
|
2014-07-30 10:31:26 +08:00 |
Florent Kermarrec
|
9cf204598a
|
mibuild/xilinx_vivado: allow sharing Misc constraints with ISE: example: ISE: DIFF_TERM=True VIVADO: set property DIFF_TERM TRUE
|
2014-07-30 10:10:41 +08:00 |